公开(公告)号：US10553574B2

公开(公告)日：2020-02-04

申请号：US15298586

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Woo Seo ,  Jin Tae Kim ,  Tae Joong Song ,  Hyoung-Suk Oh ,  Keun Ho Lee ,  Dal Hee Lee ,  Sung We Cho

IPC: H01L27/02 ,  H01L21/8234 ,  H01L23/528 ,  H01L21/67 ,  H01L23/522 ,  H01L27/088 ,  H03K19/177 ,  H03K19/00 ,  H03K19/20 ,  H03K19/21

Abstract: An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.

公开(公告)号：US10020048B2

公开(公告)日：2018-07-10

申请号：US15361599

申请日：2016-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin Rim ,  Tae Joong Song ,  Yong Ho Kim ,  Sung Hyun Park

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/418 ,  G06F1/32 ,  G11C8/08

CPC classification number: G11C11/419 ,  G06F1/3275 ,  G11C8/08 ,  G11C11/418 ,  Y02D10/14

Abstract: An integrated circuit (IC) and a mobile device are provided. The IC includes a memory cell that includes a word line, a bit line pair, and a storage cell connected to the word line and the bit line pair. The IC further includes a timing control circuit configured to generate switch signals based on an operation control signal, and a switch circuit configured to receive a first voltage, a second voltage and a third voltage having different levels, and output, to the word line, one among the first voltage, the second voltage, and the third voltage based on the switch signals.

公开(公告)号：US20140101395A1

公开(公告)日：2014-04-10

申请号：US14038932

申请日：2013-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Joong Song ,  Gyu Hong Kim ,  Jae Ho Park ,  Gi Young Yang ,  Jong Hoon Jung

IPC: G11C7/12 ,  G06F12/00

CPC classification number: G11C7/12 ,  G06F12/00 ,  G11C11/419

Abstract: Semiconductor memory devices are provided. Each of the semiconductor memory devices may include first and second memory cells. The first memory cell may be connected to a bit line and a complementary bit line. Moreover, each of the semiconductor memory devices may include a discharge circuit connected to the first memory cell via the bit line and the complementary bit line. The discharge circuit may be configured to discharge the first memory cell during a read or write operation of the second memory cell.

Abstract translation: 提供半导体存储器件。 每个半导体存储器件可以包括第一和第二存储单元。 第一存储单元可以连接到位线和互补位线。 此外，每个半导体存储器件可以包括通过位线和互补位线连接到第一存储单元的放电电路。 放电电路可以被配置为在第二存储单元的读取或写入操作期间对第一存储单元进行放电。

公开(公告)号：US11031385B2

公开(公告)日：2021-06-08

申请号：US16725023

申请日：2019-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Woo Seo ,  Jin Tae Kim ,  Tae Joong Song ,  Hyoung-Suk Oh ,  Keun Ho Lee ,  Dal Hee Lee ,  Sung We Cho

IPC: H01L27/02 ,  H01L27/088 ,  H01L21/67 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H03K19/17736 ,  H03K19/17764 ,  H01L27/118 ,  H01L27/092 ,  H03K19/00 ,  H03K19/20 ,  H03K19/21

Abstract: An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.

公开(公告)号：US09087566B2

公开(公告)日：2015-07-21

申请号：US14038932

申请日：2013-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Joong Song ,  Gyu Hong Kim ,  Jae Ho Park ,  Gi Young Yang ,  Jong Hoon Jung

IPC: G06F12/00 ,  G11C7/12 ,  G11C11/419

CPC classification number: G11C7/12 ,  G06F12/00 ,  G11C11/419

Abstract: Semiconductor memory devices are provided. Each of the semiconductor memory devices may include first and second memory cells. The first memory cell may be connected to a bit line and a complementary bit line. Moreover, each of the semiconductor memory devices may include a discharge circuit connected to the first memory cell via the bit line and the complementary bit line. The discharge circuit may be configured to discharge the first memory cell during a read or write operation of the second memory cell.

Abstract translation: 提供半导体存储器件。 每个半导体存储器件可以包括第一和第二存储单元。 第一存储单元可以连接到位线和互补位线。 此外，每个半导体存储器件可以包括通过位线和互补位线连接到第一存储单元的放电电路。 放电电路可以被配置为在第二存储单元的读取或写入操作期间对第一存储单元进行放电。