Invention Grant
- Patent Title: Lithography model calibration
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Application No.: US16748551Application Date: 2020-01-21
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Publication No.: US11061318B2Publication Date: 2021-07-13
- Inventor: Shih-Hsiang Lo , Hsu-Ting Huang , Ru-Gun Liu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: G06F111/06
- IPC: G06F111/06 ; G06F111/10 ; G03F1/36 ; G03F1/70 ; H01L21/027 ; G03F7/20

Abstract:
Provided is a method for fabricating a semiconductor device including generating an ideal image using measured contour data and fitted conventional model terms. The method further includes using the fitted conventional model terms and a mask layout to provide a conventional model aerial image. In some embodiments, the method further includes generating a plurality of mask raster images using the mask layout, where the plurality of mask raster images is generated for each measurement site of the measured contour data. In various embodiments, the method also include training a neural network to mimic the ideal image, where the generated ideal image provides a target output of the neural network, and where the conventional model aerial image and the plurality of mask raster images provide inputs to the neural network.
Public/Granted literature
- US20200278604A1 LITHOGRAPHY MODEL CALIBRATION Public/Granted day:2020-09-03
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