公开(公告)号：US10942443B2

公开(公告)日：2021-03-09

申请号：US16144882

申请日：2018-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Ting Huang ,  Shih-Hsiang Lo ,  Ru-Gun Liu

IPC: G03F1/36 ,  G03F1/78

Abstract: A method for mask data synthesis and mask making includes calibrating an optical proximity correction (OPC) model by adjusting a plurality of parameters including a first parameter and a second parameter, wherein the first parameter indicates a long-range effect caused by an electron-beam lithography tool for making a mask used to manufacture a structure, and the second parameter indicates a geometric feature of a structure or a manufacturing process to make the structure, generating a device layout, calculating a first grid pattern density map of the device layout, generating a long-range correction map, at least based on the calibrated OPC model and the first grid pattern density map of the device layout, and performing an OPC to generate a corrected mask layout, at least based on the generated long-range correction map and the calibrated OPC model.

公开(公告)号：US11092899B2

公开(公告)日：2021-08-17

申请号：US16698044

申请日：2019-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Ting Huang ,  Tung-Chin Wu ,  Shih-Hsiang Lo ,  Chih-Ming Lai ,  Jue-Chin Yu ,  Ru-Gun Liu ,  Chin-Hsiang Lin

IPC: G06F30/398 ,  G06F30/392 ,  G03F7/20 ,  G06F16/23 ,  G06N3/08 ,  G06N3/04

Abstract: A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.

公开(公告)号：US11415890B2

公开(公告)日：2022-08-16

申请号：US17195469

申请日：2021-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Ting Huang ,  Shih-Hsiang Lo ,  Ru-Gun Liu

IPC: G03F7/20 ,  G03F1/36 ,  G03F1/78

Abstract: A method for mask data synthesis and mask making includes calibrating an optical proximity correction (OPC) model by adjusting a plurality of parameters including a first parameter and a second parameter, wherein the first parameter indicates a long-range effect caused by an electron-beam lithography tool for making a mask used to manufacture a structure, and the second parameter indicates a geometric feature of a structure or a manufacturing process to make the structure, generating a device layout, calculating a first grid pattern density map of the device layout, generating a long-range correction map, at least based on the calibrated OPC model and the first grid pattern density map of the device layout, and performing an OPC to generate a corrected mask layout, at least based on the generated long-range correction map and the calibrated OPC model.

公开(公告)号：US11080458B2

公开(公告)日：2021-08-03

申请号：US16584396

申请日：2019-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fu An Tien ,  Hsu-Ting Huang ,  Ru-Gun Liu ,  Shih-Hsiang Lo

IPC: G06F30/30 ,  G06F30/398 ,  G03F7/20 ,  G01N21/95 ,  G03F1/36 ,  G06F30/3308 ,  G06F30/337 ,  G06F30/20 ,  G06F119/18 ,  G03F1/70

Abstract: In a method of optimizing a lithography model in a lithography simulation, a mask is formed in accordance with a given layout, a wafer is printed using the mask, a pattern formed on the printed wafer is measured, a wafer pattern is simulated using a wafer edge bias table and the given mask layout, a difference between the simulated wafer pattern and the measured pattern is obtained, and the wafer edge table is adjusted according to the difference.

公开(公告)号：US11061318B2

公开(公告)日：2021-07-13

申请号：US16748551

申请日：2020-01-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hsiang Lo ,  Hsu-Ting Huang ,  Ru-Gun Liu

IPC: G06F111/06 ,  G06F111/10 ,  G03F1/36 ,  G03F1/70 ,  H01L21/027 ,  G03F7/20

Abstract: Provided is a method for fabricating a semiconductor device including generating an ideal image using measured contour data and fitted conventional model terms. The method further includes using the fitted conventional model terms and a mask layout to provide a conventional model aerial image. In some embodiments, the method further includes generating a plurality of mask raster images using the mask layout, where the plurality of mask raster images is generated for each measurement site of the measured contour data. In various embodiments, the method also include training a neural network to mimic the ideal image, where the generated ideal image provides a target output of the neural network, and where the conventional model aerial image and the plurality of mask raster images provide inputs to the neural network.