- 专利标题： First layer interconnect first on carrier approach for EMIB patch
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申请号： US16646084申请日： 2018-01-12
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公开(公告)号： US11088103B2公开(公告)日： 2021-08-10
- 发明人: Changhua Liu , Xiaoying Guo , Aleksandar Aleksov , Steve S. Cho , Leonel Arana , Robert May , Gang Duan
- 申请人： Intel Corporation
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Schwabe, Williamson & Wyatt P.C.
- 国际申请： PCT/US2018/013620 WO 20180112
- 国际公布： WO2019/139625 WO 20190718
- 主分类号： H01L23/52
- IPC分类号： H01L23/52 ; H01L23/00
摘要：
A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.
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