公开(公告)号：US20250006665A1

公开(公告)日：2025-01-02

申请号：US18883825

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Gang Duan ,  Minglu Liu ,  Srinivas Venkata Ramanuja Pietambaram

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498 ,  H01L23/535 ,  H01L25/11 ,  H01L25/18 ,  H01L29/66

Abstract: Systems, apparatus, articles of manufacture, and methods for stacks of glass layers including deep trench capacitors are disclosed. An example substrate for an integrated circuit package disclosed herein includes a first glass layer, a second glass layer coupled to the first glass layer, and a deep trench capacitor embedded in the first core.

公开(公告)号：US20250006611A1

公开(公告)日：2025-01-02

申请号：US18883786

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Minglu Liu

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/64 ,  H01L25/065

Abstract: Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example integrated circuit (IC) package includes: a package core including a first glass sheet and a second glass sheet distinct from the first glass sheet, the first glass sheet having a different coefficient of thermal expansion (CTE) from the second glass sheet; a first redistribution layer on a first side of the package core; a second redistribution layer on a second side of the package core, the second side opposite the first side; and an interconnect extending through the package core, the interconnect including a magnetic material.

公开(公告)号：US20250006610A1

公开(公告)日：2025-01-02

申请号：US18883781

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Minglu Liu

IPC: H01L23/498 ,  H01L23/15 ,  H01L25/065

Abstract: Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (CTE); a second glass layer having a second CTE, the second CTE different from the first CTE; and a magnetic material lining a first wall of a first opening in the first glass layer and lining a second wall of a second opening in the second glass layer.

公开(公告)号：US20240355749A1

公开(公告)日：2024-10-24

申请号：US18756580

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Gang Duan ,  Jefferson Coker Kaplan ,  Brandon Christian Marin ,  Srinivas Venkata Ramanuja Pietambaram

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L25/16

CPC classification number: H01L23/5385 ,  H01L23/15 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/162 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Disaggregated package substrates with glass cores are disclosed. An example package substrate includes a glass core having a first side and a second side opposite the first side. The example package substrate further includes a first block of redistribution layers on the first side of the glass core. The example package substrate also includes a second block of redistribution layers on the first side of the glass core. The first block is distinct from the second block.

公开(公告)号：US20240332134A1

公开(公告)日：2024-10-03

申请号：US18193182

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Liang He ,  Jung Kyu Han ,  Gang Duan

IPC: H01L23/495 ,  H01L21/768 ,  H01L23/00 ,  H01L23/15 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/49513 ,  H01L21/76898 ,  H01L23/15 ,  H01L23/5283 ,  H01L23/53228 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/05147 ,  H01L2224/06131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131

Abstract: Methods and apparatus to mitigate electromigration are disclosed. A disclosed example integrated circuit (IC) package includes a dielectric substrate, a contact pad at least partially extending though or positioned on the dielectric substrate, the contact pad including copper, and a metal interconnect coupled to the contact pad, the interconnect including indium.

公开(公告)号：US20240222249A1

公开(公告)日：2024-07-04

申请号：US18148355

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Srinivas V. Pietambaram ,  Gang Duan ,  Brandon Christian Marin ,  Suddhasattwa Nad ,  Oladeji T. Fadayomi ,  Manuel Gadogbe ,  Matthew L. Tingey

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227

Abstract: In one embodiment, an integrated circuit package substrate includes a glass layer having at least one roughened surface (e.g., with an average roughness above 100 nm) and a metal (e.g., a metal trace or metal via) in contact with the roughened surface of the glass layer.

公开(公告)号：US20240222248A1

公开(公告)日：2024-07-04

申请号：US18147457

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Brandon Christian Marin ,  Sashi Shekhar Kandanur ,  Srinivas V. Pietambaram ,  Gang Duan ,  Jeremy D. Ecton

IPC: H01L23/498 ,  H01L21/306

CPC classification number: H01L23/49827 ,  H01L21/30604 ,  H01L23/49822 ,  H01L23/49866 ,  H01L21/78

Abstract: Architectures and methods for metal lamination on a glass layer or glass core. The architectures implement dummy anchors to prevent or reduce the delamination of conductive materials from glass surfaces. The anchors hold the conductive pads and conductive material planes down to the glass surface. The architecture includes various combinations of end anchors and through glass via (TGV) anchors.

公开(公告)号：US20240222243A1

公开(公告)日：2024-07-04

申请号：US18091555

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Bai Nie ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu ,  Kristof Darmawikarta

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16227

Abstract: An integrated circuit device substrate includes a first glass layer with a redistribution layer mounting region and an integrated circuit device mounting region, wherein a first major surface of the first glass layer is overlain by a first dielectric layer, and wherein the first glass layer includes a first plurality of conductive pillars. A second glass layer is on the redistribution layer mounting region on the first glass layer, wherein the second glass layer includes a second dielectric layer on a second major surface thereof, and wherein the second dielectric layer is bonded to the first dielectric layer on the first major surface of the first glass layer, the second glass layer including a second plurality of conductive pillars electrically interconnected with the first plurality of conductive pillars in the first glass layer.

公开(公告)号：US20240222139A1

公开(公告)日：2024-07-04

申请号：US18090879

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Brandon Marin ,  Gang Duan ,  Jeremy Ecton ,  Srinivas Pietambaram

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/495 ,  H01L25/065

CPC classification number: H01L21/4842 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16258

Abstract: Microelectronic integrated circuit package structures include a solder joint structure having a first portion on a die and a second portion on a substrate. The first portion comprises a first metal. An inner portion of the second portion comprises a second metal, and an outer portion of the second portion comprises an intermetallic compound (IMC) of the first and second metals.

公开(公告)号：US20240222035A1

公开(公告)日：2024-07-04

申请号：US18090305

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Kristof Darmawikarta ,  Benjamin Duong ,  Gang Duan ,  Srinivas Pietambaram ,  Brandon Marin ,  Jeremy Ecton ,  Jason Steill ,  Thomas Sounart ,  Darko Grujicic

IPC: H01G4/33 ,  H01G4/012 ,  H01G4/252 ,  H01L21/48 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01G4/33 ,  H01G4/012 ,  H01G4/252 ,  H01L21/486 ,  H01L23/49827 ,  H01L25/165 ,  H01L23/3675

Abstract: Apparatuses, capacitor structures, assemblies, and techniques related to package substrate embedded capacitors are described. A capacitor architecture includes a multi-layer capacitor structure at least partially within an opening extending through an insulative material layer of a package substrate or on a package substrate. The multi-layer capacitor structure includes at least two capacitor dielectric layers interleaved with a plurality of conductive layers such that the capacitor dielectric layers are at least partially within the opening and one of the conductive layers are on a sidewall of the opening.