公开(公告)号：US20240071777A1

公开(公告)日：2024-02-29

申请号：US18502244

申请日：2023-11-06

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Robert May ,  Sri Ranga Sai Boyapati ,  Srinivas V. Pietambaram ,  Chung Kwang Christopher Tan ,  Aleksandar Aleksov

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L21/481 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838

Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, a method for forming an IC package support may include forming a first dielectric material having a surface; forming a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees relative to the surface of the first dielectric material; forming a second dielectric material, having a surface, on the first dielectric material; and forming a second conductive via in the second dielectric material, wherein the second conductive via is electrically coupled to the first conductive via, has tapered sidewalls with an angle that is greater than 80 degrees relative to the surface of the second dielectric material, and a maximum diameter between 2 microns and 20 microns.

公开(公告)号：US20250022786A1

公开(公告)日：2025-01-16

申请号：US18899851

申请日：2024-09-27

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Hiroki Tanaka ,  Haobo Chen ,  Brandon Christian Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Jason Gamba ,  Bohan Shan ,  Robert May ,  Benjamin Taylor Duong ,  Bai Nie ,  Whitney Bryks

IPC: H01L23/498 ,  H01L23/08

Abstract: Methods and apparatus for edge protected glass cores are disclosed herein. An example package substrate includes a first glass layer including a first surface, a second surface opposite the first surface, and first lateral surfaces extending between the first and second surfaces, the first glass layer having a first via extending between the first surface and the second surface; and a dielectric material in contact with the first surface of the first glass layer and in contact with the first lateral surfaces of the first glass layer.

公开(公告)号：US11309192B2

公开(公告)日：2022-04-19

申请号：US16000205

申请日：2018-06-05

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Robert May ,  Sri Ranga Sai Boyapati ,  Srinivas V. Pietambaram ,  Chung Kwang Christopher Tan ,  Aleksandar Aleksov

IPC: H01L21/48 ,  H01L23/498

Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.

公开(公告)号：US11088103B2

公开(公告)日：2021-08-10

申请号：US16646084

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Changhua Liu ,  Xiaoying Guo ,  Aleksandar Aleksov ,  Steve S. Cho ,  Leonel Arana ,  Robert May ,  Gang Duan

IPC: H01L23/52 ,  H01L23/00

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

公开(公告)号：US20250069902A1

公开(公告)日：2025-02-27

申请号：US18945842

申请日：2024-11-13

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Robert May ,  Sri Ranga Sai Boyapati ,  Srinivas V. Pietambaram ,  Chung Kwang Christopher Tan ,  Aleksandar Aleksov

IPC: H01L21/48 ,  H01L23/498

Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, a method for forming an IC package support may include forming a first dielectric material having a surface; forming a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees relative to the surface of the first dielectric material; forming a second dielectric material, having a surface, on the first dielectric material; and forming a second conductive via in the second dielectric material, wherein the second conductive via is electrically coupled to the first conductive via, has tapered sidewalls with an angle that is greater than 80 degrees relative to the surface of the second dielectric material, and a maximum diameter between 2 microns and 20 microns.

公开(公告)号：US20240329333A1

公开(公告)日：2024-10-03

申请号：US18129690

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Robert May ,  Bai Nie ,  Changhua Liu ,  Hiroki Tanaka ,  Kristof Darmawikarta ,  Lilia May ,  Shriya Seshadri ,  Srinivas Pietambaram ,  Tarek Ibrahim

IPC: G02B6/42 ,  G02B6/13 ,  H01L25/065 ,  H01L25/16

CPC classification number: G02B6/4202 ,  G02B6/13 ,  H01L25/0655 ,  H01L25/167 ,  G02B2006/12038

Abstract: Multi-die packages including both photonic and electric integrated circuit (IC) die interconnected to each other through a routing structure built-up on a glass substrate. A glass preform comprising an optical waveguide may also be attached to the routing structure. A plurality of electrical IC (EIC) die may be arrayed over the routing structure along with a plurality of photonic IC (PIC). Each PIC may be coupled to an optical waveguide within the glass preform. Conductive vias may extend through the glass substrate and be further coupled with a host substrate. The host substrate may comprise glass and an optical waveguide embedded within the glass. A vertical coupler may be attached to the host substrate to optically couple the host substrate to the optical waveguide within the glass preform of the multi-die package. Many of the multi-die packages may be arrayed over a routing structure on the host substrate.

公开(公告)号：US20240321657A1

公开(公告)日：2024-09-26

申请号：US18189782

申请日：2023-03-24

Applicant: Intel Corporation

Inventor： Darko Grujicic ,  Suddhasattwa Nad ,  Srinivas Pietambaram ,  Rengarajan Shanmugam ,  Marcel Wall ,  Sashi Kandanur ,  Rahul Manepalli ,  Robert May

IPC: H01L23/15 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L23/49827 ,  H01L23/49866 ,  G02B6/4214

Abstract: Photonic integrated circuit packages and methods of manufacturing are disclosed. An example integrated circuit package includes: a semiconductor die; a package substrate supporting the semiconductor die, the package substrate including a glass core, the glass core including a through glass via extending between opposing first and second surfaces of the glass core, the glass core including a recess spaced apart from the through glass via, the recess defined by a third surface of the glass core, the recess having a different shape than the through glass via; and a reflective metal disposed on the third surface to define a mirror, the reflective metal also disposed between a wall of the through glass via and a conductive material disposed in the through glass via.

公开(公告)号：US11322444B2

公开(公告)日：2022-05-03

申请号：US15934343

申请日：2018-03-23

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Hiroki Tanaka ,  Robert May ,  Sameer Paital ,  Bai Nie ,  Jesse Jones ,  Chung Kwang Christopher Tan

IPC: H01L23/538 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065

Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

公开(公告)号：US12148703B2

公开(公告)日：2024-11-19

申请号：US18135067

申请日：2023-04-14

Applicant: Intel Corporation

Inventor： Robert Sankman ,  Robert May

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages for PoINT architectures. Particularly, embodiments include electronic packages that include reinforcement substrates to minimize warpage. In an embodiment, an electronic package comprises, a reinforcement substrate, a plurality of through substrate vias through the reinforcement substrate, a dielectric substrate over the reinforcement substrate, a cavity into the dielectric substrate, and a component in the cavity.

公开(公告)号：US11935857B2

公开(公告)日：2024-03-19

申请号：US17952080

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Kristof Darmawaikarta ,  Robert May ,  Sashi Kandanur ,  Sri Ranga Sai Boyapati ,  Srinivas Pietambaram ,  Steve Cho ,  Jung Kyu Han ,  Thomas Heaton ,  Ali Lehaf ,  Ravindranadh Eluri ,  Hiroki Tanaka ,  Aleksandar Aleksov ,  Dilan Seneviratne

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L24/17 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/11 ,  H01L2924/01029 ,  H01L2924/0105

Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).