Invention Grant
- Patent Title: Three-dimensional memory devices containing structures for controlling gate-induced drain leakage current and method of making the same
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Application No.: US16800097Application Date: 2020-02-25
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Publication No.: US11121153B1Publication Date: 2021-09-14
- Inventor: Tomoyuki Obu , Shinsuke Yada
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: US TX Addison
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Addison
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L27/11582 ; H01L29/66 ; H01L27/11519 ; H01L29/10 ; H01L29/06 ; H01L21/311 ; H01L21/28 ; H01L21/02 ; H01L27/11573 ; H01L27/11575 ; H01L27/11526 ; H01L27/11548 ; H01L27/11556 ; H01L27/11565 ; H01L29/423 ; H01L29/788 ; H01L29/792 ; H01L29/417

Abstract:
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack. A layer stack including a charge storage layer, a tunneling dielectric layer, a semiconductor material layer, and a dielectric material layer is formed in the memory openings. The dielectric material layer may include a doped silicate glass layer. A doped silicate glass pillar can be formed at a bottom portion of each memory opening, and a bottom portion of the semiconductor material layer can be converted into a source region by outdiffusion of dopants from the doped silicate glass pillar. Alternatively, the semiconductor material layer can be heavily doped, and can be recessed to form a source region.
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