Invention Grant
- Patent Title: Recessed inductor structure to reduce step height
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Application No.: US16589395Application Date: 2019-10-01
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Publication No.: US11139239B2Publication Date: 2021-10-05
- Inventor: Hung-Wen Hsu , Jiech-Fun Lu , Kai Tzeng , Wei-Li Huang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L49/02 ; H01L21/768 ; H01L23/532 ; H01L23/528

Abstract:
Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including an interconnect structure overlying a substrate. The interconnect structure has a plurality of metal layers overlying over the substrate. A first dielectric layer overlies an uppermost surface of the interconnect structure. The first dielectric layer has opposing sidewalls defining a trench. A first magnetic layer is disposed within the trench and conformally extends along the opposing sidewalls. Conductive wires are disposed within the trench and overlie the first magnetic layer. A second magnetic layer overlies the first magnetic layer and the conductive wires. The second magnetic layer laterally extends from over a first sidewall of the opposing sidewalls to a second sidewall of the opposing sidewalls.
Public/Granted literature
- US20210098371A1 RECESSED INDUCTOR STRUCTURE TO REDUCE STEP HEIGHT Public/Granted day:2021-04-01
Information query
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