公开(公告)号：US11776985B2

公开(公告)日：2023-10-03

申请号：US17313140

申请日：2021-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsun-Kai Tsao ,  Jiech-Fun Lu ,  Shih-Pei Chou ,  Wei Chuang Wu

IPC: H01L27/146

CPC classification number: H01L27/14685 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14623

Abstract: A method of fabricating self-aligned grids in a BSI image sensor is provided. The method includes depositing a first dielectric layer over a back surface of a substrate that has a plurality of photodiodes formed therein, forming a grid of trenches, and filling in the trenches with dielectric material to create a trench isolation grid. Here, a trench passes through the first dielectric layer and extends into the substrate. The method further includes etching back dielectric material in the trenches to a level that is below an upper surface of the first dielectric layer to form recesses overlaying the trench isolation grid, and filling in the recesses with metallic material to create a metallic grid that is aligned with the trench isolation grid.

公开(公告)号：US11139239B2

公开(公告)日：2021-10-05

申请号：US16589395

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Wen Hsu ,  Jiech-Fun Lu ,  Kai Tzeng ,  Wei-Li Huang

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including an interconnect structure overlying a substrate. The interconnect structure has a plurality of metal layers overlying over the substrate. A first dielectric layer overlies an uppermost surface of the interconnect structure. The first dielectric layer has opposing sidewalls defining a trench. A first magnetic layer is disposed within the trench and conformally extends along the opposing sidewalls. Conductive wires are disposed within the trench and overlie the first magnetic layer. A second magnetic layer overlies the first magnetic layer and the conductive wires. The second magnetic layer laterally extends from over a first sidewall of the opposing sidewalls to a second sidewall of the opposing sidewalls.

公开(公告)号：US20210280630A1

公开(公告)日：2021-09-09

申请号：US17313140

申请日：2021-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsun-Kai Tsao ,  Jiech-Fun Lu ,  Shih-Pei Chou ,  Wei Chuang Wu

IPC: H01L27/146

Abstract: A method of fabricating self-aligned grids in a BSI image sensor is provided. The method includes depositing a first dielectric layer over a back surface of a substrate that has a plurality of photodiodes formed therein, forming a grid of trenches, and filling in the trenches with dielectric material to create a trench isolation grid. Here, a trench passes through the first dielectric layer and extends into the substrate. The method further includes etching back dielectric material in the trenches to a level that is below an upper surface of the first dielectric layer to form recesses overlaying the trench isolation grid, and filling in the recesses with metallic material to create a metallic grid that is aligned with the trench isolation grid.

公开(公告)号：US20210272996A1

公开(公告)日：2021-09-02

申请号：US16848903

申请日：2020-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsun-Kai Tsao ,  Cheng-Hsien Chou ,  Jiech-Fun Lu

IPC: H01L27/146

Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed within a substrate. The substrate has a front-side surface and a back-side surface. An absorption enhancement structure is disposed along the back-side surface of the substrate and overlies the photodetector. The absorption enhancement structure includes a plurality of protrusions that extend outwardly from the back-side surface of the substrate. Each protrusion comprises opposing curved sidewalls.

公开(公告)号：US20210098371A1

公开(公告)日：2021-04-01

申请号：US16589395

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Wen Hsu ,  Jiech-Fun Lu ,  Kai Tzeng ,  Wei-Li Huang

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including an interconnect structure overlying a substrate. The interconnect structure has a plurality of metal layers overlying over the substrate. A first dielectric layer overlies an uppermost surface of the interconnect structure. The first dielectric layer has opposing sidewalls defining a trench. A first magnetic layer is disposed within the trench and conformally extends along the opposing sidewalls. Conductive wires are disposed within the trench and overlie the first magnetic layer. A second magnetic layer overlies the first magnetic layer and the conductive wires. The second magnetic layer laterally extends from over a first sidewall of the opposing sidewalls to a second sidewall of the opposing sidewalls.

公开(公告)号：US20200258989A1

公开(公告)日：2020-08-13

申请号：US16861478

申请日：2020-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuo-Hwa Tzeng ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC: H01L29/40 ,  H01L21/311 ,  H01L21/66 ,  H01L21/324 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762

Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

公开(公告)号：US20190057994A1

公开(公告)日：2019-02-21

申请号：US15935341

申请日：2018-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Huang ,  Jiech-Fun Lu ,  Yu-Chun Chen

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.

公开(公告)号：US20180061877A1

公开(公告)日：2018-03-01

申请号：US15803995

申请日：2017-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Wen-I Hsu ,  Tsun-Kai Tsao ,  Chih-Yu Lai ,  Jiech-Fun Lu ,  Yeur-Luen Tu

IPC: H01L27/146 ,  H01L31/18

CPC classification number: H01L27/14614 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/18

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate, and selectively forming a gate material over the gate dielectric layer. A gate dielectric protection layer is formed over the gate dielectric layer, and a first sidewall spacer is formed over the gate dielectric protection layer and flanking a side of the gate material. The gate dielectric protection layer continuously extends from between the first sidewall spacer and the gate dielectric layer to outside of the first sidewall spacer.

公开(公告)号：US20220230939A1

公开(公告)日：2022-07-21

申请号：US17150048

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Ling Shih ,  Ming Chyi Liu ,  Jiech-Fun Lu

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/146

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) including a conductive structure disposed within a dielectric structure along a first side of a semiconductor substrate, an insulating structure disposed along inner sidewalls of the semiconductor substrate, the inner sidewalls of the semiconductor substrate extending through the semiconductor substrate, a blocking layer disposed along inner sidewalls of the insulating structure, and a through-substrate via (TSV) comprising a first portion and a second portion, the first portion extending from a second side of the semiconductor substrate to a horizontally-extending surface of the insulating structure that protrudes outward from the inner sidewalls of the insulating structure, the second portion extending from the first portion to the conductive structure and has a maximum width less than that of the first portion.

公开(公告)号：US11315972B2

公开(公告)日：2022-04-26

申请号：US17095994

申请日：2020-11-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Wen Hsu ,  Jiech-Fun Lu ,  Yeur-Luen Tu ,  U-Ting Chen ,  Shu-Ting Tsai ,  Hsiu-Yu Cheng

IPC: H01L27/14 ,  H01L27/146

Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A method includes forming a plurality of photosensitive pixels in a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface, the substrate having one or more active devices on the first surface. A first portion of the second surface is protected. A second portion of the second surface is patterned to form recesses in the substrate. An anti-reflective layer is formed on sidewalls of the recesses. A metal grid is formed over the second portion of the second surface, the anti-reflective layer being interposed between the substrate and the metal grid.