Invention Grant
- Patent Title: Parasitic capacitance reduction
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Application No.: US17085032Application Date: 2020-10-30
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Publication No.: US11302802B2Publication Date: 2022-04-12
- Inventor: Jia-Heng Wang , Chun-Han Chen , I-Wen Wu , Chen-Ming Lee , Fu-Kai Yang , Mei-Yun Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L29/66 ; H01L29/06 ; H01L21/3213 ; H01L21/8234 ; H01L29/78

Abstract:
The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottommost surface of the gate structure is closer to the substrate than a bottommost surface of the source/drain contact.
Public/Granted literature
- US20210257483A1 Parasitic Capacitance Reduction Public/Granted day:2021-08-19
Information query
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