Invention Grant
- Patent Title: Hybrid bonding technology for stacking integrated circuits
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Application No.: US16902539Application Date: 2020-06-16
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Publication No.: US11322481B2Publication Date: 2022-05-03
- Inventor: Kuo-Ming Wu , Ching-Chun Wang , Dun-Nian Yaung , Hsing-Chih Lin , Jen-Cheng Liu , Min-Feng Kao , Yung-Lung Lin , Shih-Han Huang , I-Nan Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/528 ; H01L23/48 ; H01L23/532 ; H01L25/00 ; H01L23/00

Abstract:
A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. A third IC die is bonded to the second IC die by a second bonding structure. The second bonding structure is arranged between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. The second bonding structure further comprises conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.
Public/Granted literature
- US20200312817A1 HYBRID BONDING TECHNOLOGY FOR STACKING INTEGRATED CIRCUITS Public/Granted day:2020-10-01
Information query
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