Invention Grant
- Patent Title: Interconnect structure and method
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Application No.: US17099263Application Date: 2020-11-16
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Publication No.: US11328952B2Publication Date: 2022-05-10
- Inventor: Chia-Cheng Chou , Chih-Chien Chi , Chung-Chi Ko , Yao-Jen Chang , Chen-Yuan Kao , Kai-Shiang Kuo , Po-Cheng Shih , Tze-Liang Lee , Jun-Yi Ruan
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/8234 ; H01L23/532 ; H01L21/84 ; H01L29/66 ; H01L23/522 ; H01L23/528 ; H01L29/78 ; H01L29/08

Abstract:
A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
Public/Granted literature
- US20210074581A1 Interconnect Structure and Method Public/Granted day:2021-03-11
Information query
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