公开(公告)号：US20230369500A1

公开(公告)日：2023-11-16

申请号：US18360344

申请日：2023-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yao-Jen Chang ,  Chih-Chien Chi ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Kai-Shiang Kuo ,  Po-Cheng Shih ,  Jun-Yi Ruan

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L29/7851 ,  H01L29/66545 ,  H01L29/66795 ,  H01L21/76816 ,  H01L23/5329 ,  H01L23/528 ,  H01L23/5226 ,  H01L21/76804 ,  H01L27/0924 ,  H01L21/823821

摘要： A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

公开(公告)号：US11777035B2

公开(公告)日：2023-10-03

申请号：US17849995

申请日：2022-06-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yao-Jen Chang ,  Chih-Chien Chi ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Kai-Shiang Kuo ,  Po-Cheng Shih ,  Jun-Yi Ruan

IPC分类号： H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/7851 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/823821 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5329 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795

摘要： A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

公开(公告)号：US11652149B2

公开(公告)日：2023-05-16

申请号：US17112782

申请日：2020-12-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Wei Chang ,  Hong-Ming Wu ,  Chen-Yuan Kao ,  Li-Hsiang Chao ,  Yi-Ying Liu

IPC分类号： H01L29/417 ,  H01L29/40 ,  H01L23/538 ,  H01L23/522 ,  H01L21/768 ,  H01L21/8234

CPC分类号： H01L29/41775 ,  H01L21/76859 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/5386 ,  H01L29/401

摘要： A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening.

公开(公告)号：US11532717B2

公开(公告)日：2022-12-20

申请号：US17176020

申请日：2021-02-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chao-Hsun Wang ,  Yu-Feng Yin ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Chen-Yuan Kao

IPC分类号： H01L27/085 ,  H01L29/423 ,  H01L29/45 ,  H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66

摘要： A semiconductor structure includes a metal gate structure comprising a gate dielectric layer and a gate electrode, a conductive layer disposed over the metal gate structure, and a contact feature in direct contact with the top portion of the conductive layer, where the conductive layer includes a bottom portion disposed below a top surface of the metal gate structure and a top portion disposed over the top surface of the metal gate structure, and where the top portion laterally extends beyond a sidewall of the bottom portion.

公开(公告)号：US10998269B2

公开(公告)日：2021-05-04

申请号：US16908113

申请日：2020-06-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Jiun Liu ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L21/288 ,  H01L23/528 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/522

摘要： A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

公开(公告)号：US09564398B2

公开(公告)日：2017-02-07

申请号：US13832195

申请日：2013-03-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Jiun Liu ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Mingh-Hsing Tsai ,  Syun-Ming Jang

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L21/288 ,  H01L23/522

CPC分类号： H01L23/53238 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

摘要翻译： 描述了具有改进的金属结构的半导体结构。 半导体结构可以包括具有上表面的衬底，在上表面上的互连层，以及沉积在互连层上的附加结构。 互连层可以包括衬底上的图案化种子层，种子层上的至少两条金属线以及相邻金属线之间的电介质材料。 阻挡层可沉积在至少两条金属线上。 还描述了制造半导体结构的方法。

公开(公告)号：US20140262797A1

公开(公告)日：2014-09-18

申请号：US13858994

申请日：2013-04-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chih-Yi Chang ,  Liang-Yueh Ou Yang ,  Chen-Yuan Kao ,  Hung-Wen Su

IPC分类号： C25D5/02 ,  C25D17/00 ,  C25D5/18

CPC分类号： C25D5/02 ,  C25D3/38 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/002 ,  C25D17/007 ,  C25D17/10 ,  H01L21/2885 ,  H01L21/76877

摘要： The present disclosure relates to an electro-chemical plating (ECP) process which utilizes a dummy electrode as a cathode to perform plating for sustained idle times to mitigate additive dissociation. The dummy electrode also allows for localized plating function to improve product gapfill, and decrease wafer non-uniformity. A wide range of electroplating recipes may be applied with this strategy, comprising current plating up to approximately 200 Amps, localized plating with a resolution of approximately 1 mm, and reverse plating to remove material from the dummy electrode accumulated during the dummy plating process and replenish ionic material within the electroplating solution.

摘要翻译： 本发明涉及一种电化学电镀（ECP）工艺，其利用虚拟电极作为阴极来进行电镀以维持空闲时间以减轻附加离解。 虚拟电极还允许局部电镀功能，以改善产品间隙填充，并减少晶片的不均匀性。 可以应用这种策略的各种电镀配方，包括当前电镀高达约200安培，分辨率约为1mm的局部电镀，以及反电镀以从虚拟电镀过程中累积的虚拟电极中除去材料并补充 电镀液中的离子材料。

公开(公告)号：US20240250139A1

公开(公告)日：2024-07-25

申请号：US18438575

申请日：2024-02-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chao-Hsun Wang ,  Yu-Feng Yin ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Chen-Yuan Kao

IPC分类号： H01L29/423 ,  H01L21/28 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/42364 ,  H01L21/28026 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4925 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor structure includes a metal gate structure having a gate dielectric layer and a gate electrode. A topmost surface of the gate dielectric layer is above a topmost surface of the gate electrode. The semiconductor structure further includes a conductive layer disposed on the gate electrode of the metal gate structure, the conductive layer having a bottom portion disposed laterally between sidewalls of the gate dielectric layer and a top portion disposed above the topmost surface of the gate dielectric layer. The semiconductor structure further includes a contact feature in direct contact with the top portion of the conductive layer.

公开(公告)号：US20220359399A1

公开(公告)日：2022-11-10

申请号：US17874804

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Che Lin ,  Po-Yu Huang ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Rueijer Lin ,  Wei-Jung Lin ,  Chen-Yuan Kao

IPC分类号： H01L23/535 ,  H01L29/45 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/285 ,  H01L23/48

摘要： Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

公开(公告)号：US20210272910A1

公开(公告)日：2021-09-02

申请号：US17306784

申请日：2021-05-03

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Jiun LIU ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L21/288 ,  H01L23/528 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/522

摘要： A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.