Invention Grant
- Patent Title: Stacked silicon package assembly having thermal management
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Application No.: US16147286Application Date: 2018-09-28
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Publication No.: US11355412B2Publication Date: 2022-06-07
- Inventor: Jaspreet Singh Gandhi , Gamal Refai-Ahmed , Henley Liu , Myongseob Kim , Tien-Yu Lee , Suresh Ramalingam , Cheang-Whang Chang
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L23/367
- IPC: H01L23/367 ; H01L23/427 ; H01L25/18 ; H01L25/00 ; H01L21/48 ; H01L25/065 ; H01L25/07
Abstract:
A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.
Information query
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