公开(公告)号：US20180358280A1

公开(公告)日：2018-12-13

申请号：US15617774

申请日：2017-06-08

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Henley Liu ,  Tien-Yu Lee ,  Gamal Refai-Ahmed ,  Myongseob Kim ,  Ferdinand F. Fernandez ,  Ivor G. Barber ,  Suresh Ramalingam

IPC: H01L23/367 ,  H01L23/10 ,  H01L23/055 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00

Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.

公开(公告)号：US10319606B1

公开(公告)日：2019-06-11

申请号：US15813008

申请日：2017-11-14

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Tien-Yu Lee ,  Henley Liu ,  Ivor G. Barber ,  Suresh Ramalingam

IPC: H01L23/48 ,  H01L23/498 ,  H05K1/11 ,  H01L21/48 ,  H01L23/00 ,  H01L23/50 ,  H01L23/14

Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a package substrate having a plurality of solder balls coupled to a plurality of contact pads. The package substrate includes a solder mask having a plurality of stepped openings, a plurality of contact pads, and circuitry disposed in the package substrate and coupled to the plurality of contact pads. The solder mask defines a top side of the package substrate. The stepped openings expose the contact pads through solder mask.

公开(公告)号：US10043730B2

公开(公告)日：2018-08-07

申请号：US14867349

申请日：2015-09-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Tien-Yu Lee ,  Ferdinand F. Fernandez ,  Suresh Ramalingam ,  Ivor G. Barber ,  Inderjit Singh ,  Nael Zohni

IPC: H01L23/10 ,  H01L23/367 ,  H01L25/065 ,  H01L23/373 ,  H01L25/00 ,  H01L23/16 ,  H01L25/18 ,  H01L23/04 ,  H01L23/473 ,  H01L21/48 ,  H01L23/00 ,  H01L23/40

Abstract: A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.

公开(公告)号：US10096502B2

公开(公告)日：2018-10-09

申请号：US15360187

申请日：2016-11-23

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Mohsen H. Mardi ,  Tien-Yu Lee ,  Ivor G. Barber ,  Cheang-Whang Chang ,  Jaspreet Singh Gandhi

IPC: B23P21/00 ,  H01L21/673 ,  H01L21/67 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56

Abstract: An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.

公开(公告)号：US20180284187A1

公开(公告)日：2018-10-04

申请号：US15471390

申请日：2017-03-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Ivor G. Barber ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Tien-Yu Lee ,  Henley Liu ,  David M. Mahoney ,  Mohsen H. Mardi

IPC: G01R31/28

CPC classification number: G01R31/2891 ,  G01R31/2889

Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.

公开(公告)号：US20180144963A1

公开(公告)日：2018-05-24

申请号：US15360187

申请日：2016-11-23

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Mohsen H. Mardi ,  Tien-Yu Lee ,  Ivor G. Barber ,  Cheang-Whang Chang ,  Jaspreet Singh Gandhi

IPC: H01L21/673 ,  H01L21/67 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L21/67333 ,  H01L21/4853 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/67109 ,  H01L23/3185 ,  H01L23/3675 ,  H01L24/16 ,  H01L2224/16227

Abstract: An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.

公开(公告)号：US20170092619A1

公开(公告)日：2017-03-30

申请号：US14867349

申请日：2015-09-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Tien-Yu Lee ,  Ferdinand F. Fernandez ,  Suresh Ramalingam ,  Ivor G. Barber ,  Inderjit Singh ,  Nael Zohni

IPC: H01L25/065 ,  H01L23/06 ,  H01L23/373 ,  H01L25/00 ,  H01L23/00 ,  H01L23/10 ,  H01L23/367

CPC classification number: H01L23/373 ,  H01L21/4882 ,  H01L23/04 ,  H01L23/16 ,  H01L23/367 ,  H01L23/40 ,  H01L23/4006 ,  H01L23/473 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.

公开(公告)号：US10529645B2

公开(公告)日：2020-01-07

申请号：US15617774

申请日：2017-06-08

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Henley Liu ,  Tien-Yu Lee ,  Gamal Refai-Ahmed ,  Myongseob Kim ,  Ferdinand F. Fernandez ,  Ivor G. Barber ,  Suresh Ramalingam

IPC: H01L23/367 ,  H01L23/10 ,  H01L23/055 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.

公开(公告)号：US10527670B2

公开(公告)日：2020-01-07

申请号：US15471390

申请日：2017-03-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Ivor G. Barber ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Tien-Yu Lee ,  Henley Liu ,  David M. Mahoney ,  Mohsen H. Mardi

IPC: G01R31/28

Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.

公开(公告)号：US09204542B1

公开(公告)日：2015-12-01

申请号：US13735338

申请日：2013-01-07

Applicant: Xilinx, Inc.

Inventor： Tien-Yu Lee ,  Rafael C. Camarota

IPC: H05K1/11 ,  G06F17/50

CPC classification number: H05K1/111 ,  G06F17/5054 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/40 ,  H01L25/0655 ,  H01L2224/16227

Abstract: An apparatus includes a package substrate for a first SSIT product with a first top die configuration, wherein the package substrate is compatible with a second SSIT product with a second top die configuration, and wherein the first top die configuration is different from the second top die configuration.

Abstract translation: 一种装置包括用于具有第一顶模配置的第一SSIT产品的封装衬底，其中所述封装衬底与具有第二顶模配置的第二SSIT产品兼容，并且其中所述第一顶模配置不同于所述第二顶模 组态。