- 专利标题： Methods for reducing contact depth variation in semiconductor fabrication
-
申请号： US16688071申请日： 2019-11-19
-
公开(公告)号： US11495494B2公开(公告)日： 2022-11-08
- 发明人: Yun Lee , Chen-Ming Lee , Fu-Kai Yang , Yi-Jyun Huang , Sheng-Hsiung Wang , Mei-Yun Wang
- 申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址： TW Hsinchu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址： TW Hsinchu
- 代理机构： Haynes and Boone, LLP
- 主分类号： H01L29/417
- IPC分类号： H01L29/417 ; H01L21/768 ; H01L29/66 ; H01L21/3105 ; H01L21/02 ; H01L21/311 ; H01L23/535 ; H01L29/06 ; H01L29/78
摘要：
An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate alongside the isolation feature such that the fin extends above the isolation feature, and a dielectric layer disposed over the isolation feature. A top surface of the dielectric layer is at a same level as a top surface of the fin or below a top surface of the fin by less than or equal to 15 nanometers.
公开/授权文献
信息查询
IPC分类:
