Invention Grant
- Patent Title: Selective high-k formation in gate-last process
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Application No.: US17203306Application Date: 2021-03-16
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Publication No.: US11508583B2Publication Date: 2022-11-22
- Inventor: Yasutoshi Okuno , Teng-Chun Tsai , Ziwei Fang , Fu-Ting Yen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L29/66 ; H01L29/49 ; H01L29/78 ; H01L29/51 ; H01L21/8238

Abstract:
A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.
Public/Granted literature
- US20210225654A1 Selective High-K Formation in Gate-Last Process Public/Granted day:2021-07-22
Information query
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