公开(公告)号：US11682588B2

公开(公告)日：2023-06-20

申请号：US17347281

申请日：2021-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Long Chen ,  Yasutoshi Okuno ,  Pang-Yen Tsai

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/08 ,  H01L21/768 ,  H01L21/762 ,  H01L29/66 ,  H01L29/167

CPC classification number: H01L21/823814 ,  H01L21/76224 ,  H01L21/76832 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for forming an epitaxial source/drain structure in a semiconductor device includes providing a substrate having a plurality of fins extending from the substrate. In some embodiments, a liner layer is formed over the plurality of fins. The liner layer is patterned to expose a first group of fins of the plurality of fins in a first region. In some embodiments, a first epitaxial layer is formed over the exposed first group of fins and a barrier layer is formed over the first epitaxial layer. Thereafter, the patterned liner layer may be removed. In various examples, a second epitaxial layer is selectively formed over a second group of fins of the plurality of fins in a second region.

公开(公告)号：US11417764B2

公开(公告)日：2022-08-16

申请号：US16941035

申请日：2020-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Winnie Victoria Wei-Ning Chen ,  Pang-Yen Tsai ,  Yasutoshi Okuno

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417

Abstract: A method for reducing stress induced defects in heterogeneous epitaxial interfaces of a semiconductor device is disclosed. The method includes forming a fin structure with a fin base, a superlattice structure on the fin base, forming a polysilicon gate structure on the fin structure, forming a source/drain (S/D) opening within a portion of the fin structure uncovered by the polysilicon gate structure, modifying the first surfaces of the first layers to curve a profile of the first surfaces, depositing first, second, and third passivation layers on the first, second, and third surfaces, respectively, forming an epitaxial S/D region within the S/D opening, and replacing the polysilicon gate structure with a metal gate structure. The superlattice structure includes first and second layers with first and second lattice constants, respectively, and the first and second lattice constants are different from each other.

公开(公告)号：US11211383B2

公开(公告)日：2021-12-28

申请号：US16927799

申请日：2020-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sung-Li Wang ,  Pang-Yen Tsai ,  Yasutoshi Okuno

IPC: H01L27/092 ,  H01L29/45 ,  H01L21/8238 ,  H01L29/08 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L21/321 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311

Abstract: A semiconductor device includes first and second epitaxial structures, first and second top metal alloy layers, and first and second bottom metal alloy layers. The first and second epitaxial structures have different cross sections. The first and second top metal alloy layers are respectively in contact with the first and second epitaxial structures. The first and second bottom metal alloy layers are respectively in contact with the first and second epitaxial structures and respectively under the first and second top metal alloy layers. The first top metal alloy layer and the first bottom metal alloy layer are made of different materials.

公开(公告)号：US11201232B2

公开(公告)日：2021-12-14

申请号：US16931590

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal A. Khaderbad ,  Sung-Li Wang ,  Yasutoshi Okuno

IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L21/02 ,  H01L21/285 ,  H01L29/08

Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a source/drain structure formed adjacent to the gate structure in the substrate and a contact formed over the source/drain structure. The semiconductor structure further includes a metal-containing layer formed over the contact and a dielectric layer covering the gate structure and the metal-containing layer. The semiconductor structure further includes a first conductive structure formed through dielectric layer and the metal-containing layer and landing on the contact. In addition, a bottom surface of the metal-containing layer is higher than a top surface of the gate structure.

公开(公告)号：US20210257262A1

公开(公告)日：2021-08-19

申请号：US17306511

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal A. Khaderbad ,  Pang-Yen Tsai ,  Yasutoshi Okuno

IPC: H01L21/8238 ,  H01L29/45 ,  H01L27/092

Abstract: A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.

公开(公告)号：US20210193816A1

公开(公告)日：2021-06-24

申请号：US16721352

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peng-Wei Chu ,  Ding-Kang Shih ,  Sung-Li Wang ,  Yasutoshi Okuno

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/45 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08

Abstract: The structure of a semiconductor device with dual silicide contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming first and second fin structures on a substrate, forming first and second epitaxial regions on the first and second fin structures, respectively, forming first and second contact openings on the first and second epitaxial regions, respectively, selectively forming an oxide capping layer on exposed surfaces of the second epitaxial region, selectively forming a first metal silicide layer on exposed surfaces of the first epitaxial region, removing the oxide capping layer, and forming first and second conductive regions on the metal silicide layer and on the exposed surfaces of the second epitaxial region, respectively. The first metal silicide layer includes a first metal. The first and second conductive regions includes a second metal different from the first metal.

公开(公告)号：US10998241B2

公开(公告)日：2021-05-04

申请号：US16454871

申请日：2019-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal A. Khaderbad ,  Pang-Yen Tsai ,  Yasutoshi Okuno

IPC: H01L21/8238 ,  H01L29/45 ,  H01L27/092

Abstract: A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.

公开(公告)号：US20210082773A1

公开(公告)日：2021-03-18

申请号：US17098267

申请日：2020-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pei-Wei Lee ,  Tsung-Yu Hung ,  Pang-Yen Tsai ,  Yasutoshi Okuno

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/02

Abstract: A method includes etching a hybrid substrate to form a recess in the hybrid substrate, in which the hybrid substrate includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the first semiconductor layer, in which after the etching, a top surface of the first semiconductor layer is exposed to the recess; forming a spacer on a sidewall of the recess, in which the spacer is slanted at a first angle relative to a top surface of the first semiconductor layer; reshaping the spacer such that the a first sidewall of the reshaped spacer is slanted at a second angle relative to the top surface of the first semiconductor layer, in which the second angle is greater than the first angle; and performing a first epitaxy process to grow an epitaxy semiconductor layer in the recess after reshaping the spacer.

公开(公告)号：US20200091011A1

公开(公告)日：2020-03-19

申请号：US16454871

申请日：2019-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal A. Khaderbad ,  Pang-Yen Tsai ,  Yasutoshi Okuno

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/45

Abstract: A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.

公开(公告)号：US12132082B2

公开(公告)日：2024-10-29

申请号：US17871464

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Wei Lee ,  Yasutoshi Okuno ,  Pang-Yen Tsai

IPC: H01L21/02 ,  H01L21/66 ,  H01L29/04 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1037 ,  H01L22/12 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device according to the present disclosure includes a substrate including a plurality of atomic steps that propagate along a first direction, and a transistor disposed on the substrate. The transistor includes a channel member extending a second direction perpendicular to the first direction, and a gate structure wrapping around the channel member.