Invention Grant
- Patent Title: Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling
-
Application No.: US17098754Application Date: 2020-11-16
-
Publication No.: US11532584B2Publication Date: 2022-12-20
- Inventor: Robert Alan May , Sri Ranga Sai Boyapati , Kristof Kuwawi Darmawikarta , Srinivas V. Pietambaram , Javier Soto Gonzalez , Kwangmo Chris Lim , Aleksandar Aleksov
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Akona IP PC
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/498 ; H01L23/522 ; H01L23/13 ; H01L21/48 ; H01L25/065

Abstract:
Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.
Public/Granted literature
Information query
IPC分类: