Invention Grant
- Patent Title: Integrated circuit with single level routing
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Application No.: US16222670Application Date: 2018-12-17
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Publication No.: US11545480B2Publication Date: 2023-01-03
- Inventor: Sachin Ishwar Gojagoji , Raja Selvaraj , Jayateerth Pandurang Mathad , Sujay Kumar
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Michelle F. Murray; Frank D. Cimino
- Priority: IN201841024233 20180629
- Main IPC: H01L27/08
- IPC: H01L27/08 ; H01L27/02 ; H01L49/02 ; H01L27/10 ; H01L27/118 ; H01L27/11

Abstract:
An integrated circuit includes a substrate layer and a resistor bank in a polysilicon layer disposed on the substrate layer. The resistor bank includes a plurality of resistor elements having a body portion extending in a longitudinal direction. A metal line is disposed in a metal layer above the polysilicon layer to extend transverse to the longitudinal direction and across the body portion of a group of the plurality of resistor elements, thereby forming a first region of the resistor bank and a second region of the resistor bank. The first region is separated from the second region by the metal line. A resistor device having a predetermined resistance includes a subset of the resistor elements in the group electrically coupled together in the second region. The resistor device also includes first and second terminals located in the same first or second region of the resistor bank.
Public/Granted literature
- US20200006317A1 INTEGRATED CIRCUIT WITH SINGLE LEVEL ROUTING Public/Granted day:2020-01-02
Information query
IPC分类: