公开(公告)号：US11545480B2

公开(公告)日：2023-01-03

申请号：US16222670

申请日：2018-12-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sachin Ishwar Gojagoji ,  Raja Selvaraj ,  Jayateerth Pandurang Mathad ,  Sujay Kumar

IPC: H01L27/08 ,  H01L27/02 ,  H01L49/02 ,  H01L27/10 ,  H01L27/118 ,  H01L27/11

Abstract: An integrated circuit includes a substrate layer and a resistor bank in a polysilicon layer disposed on the substrate layer. The resistor bank includes a plurality of resistor elements having a body portion extending in a longitudinal direction. A metal line is disposed in a metal layer above the polysilicon layer to extend transverse to the longitudinal direction and across the body portion of a group of the plurality of resistor elements, thereby forming a first region of the resistor bank and a second region of the resistor bank. The first region is separated from the second region by the metal line. A resistor device having a predetermined resistance includes a subset of the resistor elements in the group electrically coupled together in the second region. The resistor device also includes first and second terminals located in the same first or second region of the resistor bank.

公开(公告)号：US11239831B2

公开(公告)日：2022-02-01

申请号：US17232982

申请日：2021-04-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sundeep Lakshmana Javvaji ,  Vinod Joseph Menezes ,  Jayateerth Pandurang Mathad

IPC: H03K19/00 ,  H03K3/356 ,  H03K19/0185 ,  H03K19/0175

Abstract: In an example, an apparatus includes a level-shifting circuit and a ramp detector. The level-shifting circuit has a current choke and a transistor coupled across the current choke, the level-shifting circuit adapted to be coupled to a first voltage source. The ramp detector has a ramp detector input adapted to be coupled to the first voltage source and a ramp detector output coupled to the transistor, the ramp detector adapted to be coupled to a second voltage source.

公开(公告)号：US20230376060A1

公开(公告)日：2023-11-23

申请号：US18361978

申请日：2023-07-31

Applicant: Texas Instruments Incorporated

Inventor： Jayateerth Pandurang Mathad ,  Rajat Chauhan

IPC: G05F1/571 ,  G05F3/24 ,  G05F1/59

CPC classification number: G05F1/571 ,  G05F3/24 ,  G05F1/59

Abstract: A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.

公开(公告)号：US11079780B2

公开(公告)日：2021-08-03

申请号：US16677284

申请日：2019-11-07

Applicant: Texas Instruments Incorporated

Inventor： Jayateerth Pandurang Mathad ,  Rajat Chauhan

IPC: G05F1/571 ,  G05F3/24 ,  G05F1/59

Abstract: A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.

公开(公告)号：US20200073423A1

公开(公告)日：2020-03-05

申请号：US16677284

申请日：2019-11-07

Applicant: Texas Instruments Incorporated

Inventor： Jayateerth Pandurang Mathad ,  Rajat Chauhan

IPC: G05F1/571 ,  G05F3/24

Abstract: A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.

公开(公告)号：US11755046B2

公开(公告)日：2023-09-12

申请号：US17353387

申请日：2021-06-21

Applicant: Texas Instruments Incorporated

Inventor： Jayateerth Pandurang Mathad ,  Rajat Chauhan

IPC: G05F1/571 ,  G05F3/24 ,  G05F1/59

CPC classification number: G05F1/571 ,  G05F1/59 ,  G05F3/24

Abstract: A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.

公开(公告)号：US20210311515A1

公开(公告)日：2021-10-07

申请号：US17353387

申请日：2021-06-21

Applicant: Texas Instruments Incorporated

Inventor： Jayateerth Pandurang Mathad ,  Rajat Chauhan

IPC: G05F1/571 ,  G05F3/24 ,  G05F1/59

Abstract: A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.

公开(公告)号：US10411690B2

公开(公告)日：2019-09-10

申请号：US15434178

申请日：2017-02-16

Applicant: Texas Instruments Incorporated

Inventor： Jayateerth Pandurang Mathad

IPC: H03K17/081 ,  H03K19/017 ,  H03K19/0175

Abstract: Disclosed examples include integrated circuits, output driver circuits and protection circuits to protect an output transistor connected between a driver output node and a first intermediate node, including a resistor connected between the output node and a gate terminal of the output transistor, a diode connected between a second intermediate node and the output transistor gate terminal, and a switching device to electrically couple the second intermediate node with a reference node to turn on the output transistor to allow a second transistor to control a voltage of the output node when a control signal is in a first state, and to disconnect the second intermediate node from the reference node to prevent current flow through the resistor to control a gate voltage of the output transistor when the control signal is in a different second state.

公开(公告)号：US20170264281A1

公开(公告)日：2017-09-14

申请号：US15434178

申请日：2017-02-16

Applicant: Texas Instruments Incorporated

Inventor： Jayateerth Pandurang Mathad

IPC: H03K17/081 ,  H03K19/0175 ,  H02M3/07

CPC classification number: H03K17/08104 ,  H03K19/017509 ,  H03K2217/0072

Abstract: Disclosed examples include integrated circuits, output driver circuits and protection circuits to protect an output transistor connected between a driver output node and a first intermediate node, including a resistor connected between the output node and a gate terminal of the output transistor, a diode connected between a second intermediate node and the output transistor gate terminal, and a switching device to electrically couple the second intermediate node with a reference node to turn on the output transistor to allow a second transistor to control a voltage of the output node when a control signal is in a first state, and to disconnect the second intermediate node from the reference node to prevent current flow through the resistor to control a gate voltage of the output transistor when the control signal is in a different second state.