Invention Grant
- Patent Title: Screening of memory circuits
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Application No.: US16817096Application Date: 2020-03-12
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Publication No.: US11568951B2Publication Date: 2023-01-31
- Inventor: Francisco Adolfo Cano , Devanathan Varadarajan , Anthony Martin Hill
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Michael T. Gabrik; Frank D. Cimino
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/38 ; G11C29/50 ; G11C11/419 ; G11C11/418 ; G11C11/412

Abstract:
Systems and methods of screening memory cells by modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven as compared to a nominal operating voltage on the wordline. In a write operation, the one or both of the bitline and wordline may be overdriven or underdriven as compared to a nominal operating voltage of each. A built-in self test (BIST) system for screening a memory array has bitline and wordline margin controls to modulate bitline and wordline voltage, respectively, in the memory array.
Public/Granted literature
- US20200294614A1 SCREENING OF MEMORY CIRCUITS Public/Granted day:2020-09-17
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