公开(公告)号：US20140159800A1

公开(公告)日：2014-06-12

申请号：US14103171

申请日：2013-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jose Luis Flores ,  Anthony Martin Hill ,  Francisco Adolfo Cano

IPC: H03K19/00

CPC classification number: H03K19/0016 ,  G01R31/31725 ,  G01R31/31727 ,  G06F1/206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A method of adaptive voltage scaling is shown incorporating a lookup table holding manufacturing characterization data in conjunction with one or more precision analog temperature sensors used for correcting for temperature effects.

Abstract translation: 示出了一种自适应电压缩放的方法，其结合了用于校正温度效应的一个或多个精密模拟温度传感器，其结合了查找表，其保存制造表征数据。

公开(公告)号：US11881275B2

公开(公告)日：2024-01-23

申请号：US18148312

申请日：2022-12-29

Applicant: Texas Instruments Incorporated

Inventor： Francisco Adolfo Cano ,  Devanathan Varadarajan ,  Anthony Martin Hill

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/50 ,  G11C11/419 ,  G11C11/418 ,  G11C11/412

CPC classification number: G11C29/38 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C29/50004 ,  G11C2029/5004

Abstract: Systems of screening memory cells of a memory include modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven with respect to a nominal operating voltage on the wordline. In a write operation, one or both of the bitline and wordline may be overdriven or underdriven with respect to corresponding a nominal operating voltage. Such a system has margin control circuity, which may be in the form of bitline and wordline margin controls, to modulate bitline and wordline voltages, respectively, in the memory cells of the memory array.

公开(公告)号：US20160308517A1

公开(公告)日：2016-10-20

申请号：US15088501

申请日：2016-04-01

Applicant: Texas Instruments Incorporated

Inventor： Anthony Martin Hill

IPC: H03K3/3562 ,  H03K3/037

CPC classification number: H03K3/35625

Abstract: The invention is an intelligent connection of the internal scan logic in a multi-bit flip-flop register. Individual bits in this register are connected in a serial scan chain. In this invention the serial chain is connection reuses logic between slave latches on bit n and master latches on bit n+1. This reuse reduces the number of transistors required to implement the multi-bit register. This reduction in the number of required transistors enables a consequent reduction in integrated circuit area required, thereby reducing manufacturing cost. Alternatively, the area saved using this invention may be used for other purposes. This could increase the value of the corresponding integrated circuit without increasing manufacturing costs.

Abstract translation: 本发明是多位触发器寄存器中的内部扫描逻辑的智能连接。 该寄存器中的各个位连接在串行扫描链中。 在本发明中，串行链路在位n上的从锁存器和位n + 1上的主锁存器之间连接重用逻辑。 这种重用减少了实现多位寄存器所需的晶体管数量。 所需晶体管数量的减少能够减少所需的集成电路面积，从而降低制造成本。 或者，使用本发明保存的区域可以用于其他目的。 这可以增加相应的集成电路的价值，而不增加制造成本。

公开(公告)号：US11568951B2

公开(公告)日：2023-01-31

申请号：US16817096

申请日：2020-03-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Francisco Adolfo Cano ,  Devanathan Varadarajan ,  Anthony Martin Hill

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/50 ,  G11C11/419 ,  G11C11/418 ,  G11C11/412

Abstract: Systems and methods of screening memory cells by modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven as compared to a nominal operating voltage on the wordline. In a write operation, the one or both of the bitline and wordline may be overdriven or underdriven as compared to a nominal operating voltage of each. A built-in self test (BIST) system for screening a memory array has bitline and wordline margin controls to modulate bitline and wordline voltage, respectively, in the memory array.

公开(公告)号：US20190229732A1

公开(公告)日：2019-07-25

申请号：US16369360

申请日：2019-03-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jose Luis Flores ,  Anthony Martin Hill ,  Francisco Adolfo Cano

IPC: H03K19/00 ,  G06F1/20 ,  G01R31/317 ,  G06F1/3296 ,  G06F1/324

Abstract: An adaptive voltage scaling technique includes using a temperature sensor arranged on a semiconductor die to determine a current die temperature of the semiconductor die, using a performance sensor arranged on a semiconductor die to determine a current performance metric of the semiconductor die, determining whether the current performance metric matches an expected performance metric based at least partially on the current die temperature and, if the current performance metric does not match the expected performance metric, indicate a performance sensor error, when a performance sensor error is indicated, determining an updated power supply voltage for correcting the performance sensor error, and causing a current power supply voltage supplied by a power supply voltage source of the semiconductor die to be changed to the updated power supply voltage.

公开(公告)号：US09490783B1

公开(公告)日：2016-11-08

申请号：US15088501

申请日：2016-04-01

Applicant: Texas Instruments Incorporated

Inventor： Anthony Martin Hill

IPC: H03K19/00 ,  H03K3/3562 ,  H03K3/037

CPC classification number: H03K3/35625

Abstract: The invention is an intelligent connection of the internal scan logic in a multi-bit flip-flop register. Individual bits in this register are connected in a serial scan chain. In this invention the serial chain is connection reuses logic between slave latches on bit n and master latches on bit n+1. This reuse reduces the number of transistors required to implement the multi-bit register. This reduction in the number of required transistors enables a consequent reduction in integrated circuit area required, thereby reducing manufacturing cost. Alternatively, the area saved using this invention may be used for other purposes. This could increase the value of the corresponding integrated circuit without increasing manufacturing costs.

Abstract translation: 本发明是多位触发器寄存器中的内部扫描逻辑的智能连接。 该寄存器中的各个位连接在串行扫描链中。 在本发明中，串行链路在位n上的从锁存器和位n + 1上的主锁存器之间连接重用逻辑。 这种重用减少了实现多位寄存器所需的晶体管数量。 所需晶体管数量的减少能够减少所需的集成电路面积，从而降低制造成本。 或者，使用本发明保存的区域可以用于其他目的。 这可以增加相应的集成电路的价值，而不增加制造成本。

公开(公告)号：US20140159801A1

公开(公告)日：2014-06-12

申请号：US14103433

申请日：2013-12-11

Applicant: Texas Instruments Incorporated

Inventor： Jose Luis Flores ,  Anthony Martin Hill ,  Francisco Adolfo Cano

IPC: H03K3/012

CPC classification number: G06F1/3296 ,  Y02D10/172

Abstract: Power consumption is reduced by the use of a plurality of parameter reference targets, optimized for a subset of the complete temperature range. The prediction accuracy of the performance tracking sensor is optimized by using small segments of the operating temperature range.

Abstract translation: 通过使用针对整个温度范围的子集而优化的多个参数参考目标来降低功耗。 通过使用工作温度范围的小段来优化性能跟踪传感器的预测精度。