- 专利标题： Stacked transistors with different gate lengths in different device strata
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申请号： US16290544申请日： 2019-03-01
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公开(公告)号： US11573798B2公开(公告)日： 2023-02-07
- 发明人: Aaron D. Lilak , Gilbert W. Dewey , Willy Rachmady , Rishabh Mehandru , Ehren Mannebach , Cheng-Ying Huang , Anh Phan , Patrick Morrow
- 申请人： Intel Corporation
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Akona IP PC
- 主分类号： H01L29/772
- IPC分类号： H01L29/772 ; G06F9/30 ; G06F9/34 ; H01L29/78 ; H01L29/66 ; H01L29/786 ; H01L29/775
摘要：
Disclosed herein are stacked transistors with different gate lengths in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, with two different device strata having different gate lengths.
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