- 专利标题: High performance phase locked loop
-
申请号: US17684273申请日: 2022-03-01
-
公开(公告)号: US11606186B2公开(公告)日: 2023-03-14
- 发明人: Armin Tajalli
- 申请人: Kandou Labs, S.A.
- 申请人地址: CH Lausanne
- 专利权人: Kandou Labs, S.A.
- 当前专利权人: Kandou Labs, S.A.
- 当前专利权人地址: CH Lausanne
- 代理机构: Invention Mine LLC
- 主分类号: H04L7/033
- IPC分类号: H04L7/033 ; H04L7/00 ; H03K3/356 ; H02M3/07 ; H03K5/26 ; H03L7/099 ; H03L7/00 ; H03L7/10
摘要:
Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.
公开/授权文献
- US20220191000A1 HIGH PERFORMANCE PHASE LOCKED LOOP 公开/授权日:2022-06-16
信息查询