Invention Grant
- Patent Title: Via contact patterning method to increase edge placement error margin
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Application No.: US17511656Application Date: 2021-10-27
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Publication No.: US11652045B2Publication Date: 2023-05-16
- Inventor: Mohit K. Haran , Daniel James Bahr , Deepak S. Rao , Marvin Young Paik , Seungdo An , Debashish Basu , Kilhyun Bang , Jason W. Klaus , Reken Patel , Charles Henry Wallace , James Jeong , Ruth Amy Brain
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Akona IP PC
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/768 ; H01L23/528 ; H01L23/532

Abstract:
An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.
Information query
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