Invention Grant
- Patent Title: III-N transistors integrated with thin-film transistors having graded dopant concentrations and/or composite gate dielectrics
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Application No.: US16367549Application Date: 2019-03-28
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Publication No.: US11652143B2Publication Date: 2023-05-16
- Inventor: Han Wui Then , Nidhi Nidhi , Paul B. Fischer , Rahul Ramaswamy , Walid M. Hafez , Samuel Jack Beach , Xiaojun Weng , Johann Christian Rode , Marko Radosavljevic , Sansaptak Dasgupta
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Akona IP PC
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L29/20 ; H01L29/786 ; H01L29/778 ; H01L29/16 ; H01L29/08 ; H01L21/8238 ; H01L27/07

Abstract:
Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N devices, e.g., III-N transistors. In various aspects, TFTs integrated with III-N transistors have a channel and source/drain materials that include one or more of a crystalline material, a polycrystalline semiconductor material, or a laminate of crystalline and polycrystalline materials. In various aspects, TFTs integrated with III-N transistors are engineered to include one or more of 1) graded dopant concentrations in their source/drain regions, 2) graded dopant concentrations in their channel regions, and 3) thicker and/or composite gate dielectrics in their gate stacks.
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