Invention Grant
- Patent Title: Method of forming a three-gate non-volatile flash memory cell using two polysilicon deposition steps
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Application No.: US17021678Application Date: 2020-09-15
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Publication No.: US11652162B2Publication Date: 2023-05-16
- Inventor: Feng Zhou , Xian Liu , Chien-Sheng Su , Nhan Do , Chunming Wang
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP (US)
- Priority: CN 1610247666.6 2016.04.20
- The original application number of the division: US16245069 2019.01.10
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/788 ; H01L27/07 ; H01L29/08 ; H01L21/28 ; H01L49/02 ; H01L29/423

Abstract:
A simplified method for forming a non-volatile memory cell using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. An insulation block is formed on the first polysilicon layer. Spacers are formed adjacent first and second sides of the insulation block, and with the spacer adjacent the first side is reduced. Exposed portions of the first poly silicon layer are removed while maintaining a polysilicon block of the first polysilicon layer disposed under the insulation block. A second polysilicon layer is formed over the substrate and the insulation block in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed adjacent the first side of the insulation block), and a second polysilicon block (disposed adjacent the second side of the insulation block).
Information query
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