Invention Grant
- Patent Title: Enabling sync header suppression latency optimization in the presence of retimers for serial interconnect
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Application No.: US17559002Application Date: 2021-12-22
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Publication No.: US11669481B2Publication Date: 2023-06-06
- Inventor: Michelle Jen , Debendra Das Sharma , Bruce Tennant , Prahladachar Jayaprakash Bharadwaj
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F13/40
- IPC: G06F13/40 ; H04L69/16 ; G06F1/3237 ; G06F13/42 ; G06F13/38

Abstract:
Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.
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