公开(公告)号：US20190303338A1

公开(公告)日：2019-10-03

申请号：US16266992

申请日：2019-02-04

申请人： Intel Corporation

发明人： Michelle Jen ,  Daniel Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC分类号： G06F13/42 ,  G06F13/40 ,  G06F13/38

摘要： An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

公开(公告)号：US20220114128A1

公开(公告)日：2022-04-14

申请号：US17559002

申请日：2021-12-22

申请人： Intel Corporation

发明人： Michelle Jen ,  Debendra Das Sharma ,  Bruce Tennant ,  Prahladachar Jayaprakash Bharadwaj

IPC分类号： G06F13/40 ,  H04L69/16 ,  G06F1/3237 ,  G06F13/42

摘要： Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.

公开(公告)号：US11232058B2

公开(公告)日：2022-01-25

申请号：US16554974

申请日：2019-08-29

申请人： Intel Corporation

发明人： Michelle Jen ,  Debendra Das Sharma ,  Bruce Tennant ,  Prahladachar Jayaprakash Bharadwaj

IPC分类号： G06F13/40 ,  G06F1/3237 ,  H04L29/06 ,  G06F13/42 ,  G06F13/38

摘要： Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.

公开(公告)号：US20220308954A1

公开(公告)日：2022-09-29

申请号：US17645828

申请日：2021-12-23

申请人： Intel Corporation

发明人： Swadesh Choudhary ,  Debendra Das Sharma ,  Michelle Jen

IPC分类号： G06F11/07 ,  G06F13/36

摘要： In an embodiment, an apparatus includes a receiver circuit to: in response to a determination that the receiver circuit is in a high latency processing mode, transmit a hint signal to a transmitter circuit; receive a response message from the transmitter circuit; process the response message to reduce a current workload of the receiver circuit; and switch the receiver circuit from the high latency processing mode to a low latency processing mode. Other embodiments are described and claimed.

公开(公告)号：US10706003B2

公开(公告)日：2020-07-07

申请号：US16266992

申请日：2019-02-04

申请人： Intel Corporation

发明人： Michelle Jen ,  Daniel Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC分类号： G06F13/38 ,  G06F13/42 ,  G06F13/40 ,  H04L29/06 ,  H04L29/08

摘要： An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

公开(公告)号：US10198394B2

公开(公告)日：2019-02-05

申请号：US15283310

申请日：2016-10-01

申请人： Intel Corporation

发明人： Michelle Jen ,  Dan Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC分类号： G06F13/00 ,  G06F13/42 ,  G06F13/38 ,  G06F13/40 ,  H04L29/06 ,  H04L29/08

摘要： An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

公开(公告)号：US20180181502A1

公开(公告)日：2018-06-28

申请号：US15387802

申请日：2016-12-22

申请人： Intel Corporation

发明人： Michelle Jen ,  Debendra Das Sharma ,  Venkatraman Iyer ,  Tao Liang

IPC分类号： G06F13/16 ,  G06F13/42 ,  G06F13/40

摘要： A retimer device receives a first signal from a first device and regenerates the first signal to send to a second device. The retimer further receive a second signal from the second device and regenerates the second signal to send to the first device, where the first device includes a processor device. The retimer includes a sideband interface to connect to the first device and further includes protocol logic to monitor the first signal, determine that the first signal includes a pattern defined in a protocol to identify a protocol activity, and participate in performance of the protocol activity using the sideband interface.

公开(公告)号：US11669481B2

公开(公告)日：2023-06-06

申请号：US17559002

申请日：2021-12-22

申请人： Intel Corporation

发明人： Michelle Jen ,  Debendra Das Sharma ,  Bruce Tennant ,  Prahladachar Jayaprakash Bharadwaj

IPC分类号： G06F13/40 ,  H04L69/16 ,  G06F1/3237 ,  G06F13/42 ,  G06F13/38

CPC分类号： G06F13/4068 ,  G06F1/3237 ,  G06F13/4291 ,  H04L69/161 ,  G06F13/385

摘要： Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.

公开(公告)号：US11163717B2

公开(公告)日：2021-11-02

申请号：US16921498

申请日：2020-07-06

申请人： Intel Corporation

发明人： Michelle Jen ,  Dan Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC分类号： G06F13/42 ,  G06F13/38 ,  G06F13/40 ,  H04L29/06 ,  H04L29/08

摘要： An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

公开(公告)号：US20210056067A1

公开(公告)日：2021-02-25

申请号：US16921498

申请日：2020-07-06

申请人： Intel Corporation

发明人： Michelle Jen ,  Dan Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC分类号： G06F13/42 ,  G06F13/38 ,  G06F13/40

摘要： An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.