According to one embodiment, a semiconductor memory device includes: a plurality of first insulating layers; a plurality of first interconnect layers stacked alternately with the first insulating layers; a plurality of second interconnect layers arranged adjacently to the first interconnect layers; and a separation region including a plurality of first portions provided between the first interconnect layers and the second interconnect layers, and a plurality of second portions protruding from an outer periphery of each of the first portions. The second portions are linked to each other. The first interconnect layers and the second interconnect layers are separated from each other by the first portions and the linked second portions.