公开(公告)号：US11862246B2

公开(公告)日：2024-01-02

申请号：US17474904

申请日：2021-09-14

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Yasuhito Yoshimizu ,  Keisuke Nakatsuka ,  Hideto Horii ,  Takashi Maeda

IPC: G11C16/04 ,  G11C16/30 ,  G11C16/32 ,  G11C5/06 ,  G11C16/26 ,  G11C5/02 ,  G11C16/10 ,  G11C16/08

CPC classification number: G11C16/0433 ,  G11C5/025 ,  G11C5/06 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

Abstract: A memory system has a memory cell array having a plurality of strings, the plurality of strings each having a plurality of memory cells connected in series, and a controller configured to perform control of transferring charges to be stored in the plurality of memory cells in the string or transferring charges according to stored data, between potential wells of channels in the plurality of memory cells.

公开(公告)号：US12131966B2

公开(公告)日：2024-10-29

申请号：US17467839

申请日：2021-09-07

Applicant: KABUSHIKI KAISHA TOSHIBA ,  Kioxia Corporation

Inventor： Fuyuma Ito ,  Yasuhito Yoshimizu ,  Nobuhito Kuge ,  Yui Kagi ,  Susumu Obata ,  Keiichiro Matsuo ,  Mitsuo Sano

IPC: H01L21/66 ,  C30B25/18 ,  H01L21/02 ,  H10B43/27

CPC classification number: H01L22/30 ,  C30B25/186 ,  H01L21/02002 ,  H01L21/02005 ,  H01L22/34 ,  H10B43/27

Abstract: A semiconductor wafer includes a surface having at least one recess including an inner wall surface. The inner wall surface is exposed.

公开(公告)号：US12057399B2

公开(公告)日：2024-08-06

申请号：US17172470

申请日：2021-02-10

Applicant: KIOXIA CORPORATION

Inventor： Yasuhito Yoshimizu

IPC: H01L27/115 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L25/065 ,  H01L25/18 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/5226 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor storage device includes a semiconductor substrate and a conductive layer separated from the semiconductor substrate in a first direction. The conductive layer extends in a second direction parallel to the semiconductor substrate. A semiconductor layer extends in the first direction through the conductive layer. A first contact extends in the first direction and is connected to a surface of the conductive layer facing away from the semiconductor substrate. A first insulating layer extends in the first direction, and a second insulating layer extends along the first insulating layer in the first direction. Each of the first and second insulating layers entirely overlaps with the first contact when viewed in the first direction.

公开(公告)号：US11672112B2

公开(公告)日：2023-06-06

申请号：US16986853

申请日：2020-08-06

Applicant: Kioxia Corporation

Inventor： Genki Kawaguchi ,  Yasuhito Yoshimizu ,  Yusuke Shima

IPC: G11C5/06 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C5/02

CPC classification number: H01L27/11556 ,  G11C5/025 ,  G11C5/06 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor memory device includes: a plurality of first insulating layers; a plurality of first interconnect layers stacked alternately with the first insulating layers; a plurality of second interconnect layers arranged adjacently to the first interconnect layers; and a separation region including a plurality of first portions provided between the first interconnect layers and the second interconnect layers, and a plurality of second portions protruding from an outer periphery of each of the first portions. The second portions are linked to each other. The first interconnect layers and the second interconnect layers are separated from each other by the first portions and the linked second portions.

公开(公告)号：US11889698B2

公开(公告)日：2024-01-30

申请号：US17190348

申请日：2021-03-02

Applicant: KIOXIA CORPORATION

Inventor： Yasuhito Yoshimizu ,  Hiroshi Nakaki ,  Kazuaki Nakajima

IPC: H10B43/35 ,  H01L23/00 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20

CPC classification number: H10B43/35 ,  H01L24/46 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20

Abstract: A semiconductor storage device includes first wiring layers stacked along a first direction, a first pillar including a first semiconductor layer and extending along the first direction through the first wiring layers, a second wiring layer disposed above the first pillar in the first direction and extending along a second direction perpendicular to the first direction, a semiconductor-containing layer including a first portion disposed on an upper end of the first pillar in the first direction, a second portion contacting the first portion and formed along the second wiring layer, and a third portion contacting an upper end of the second portion and extending along a third direction perpendicular to the first direction and crossing the second direction, and a first insulating layer between each of the first and second portions of the semiconductor-containing layer and the second wiring layer. An upper surface of the third portion contains a metal.

公开(公告)号：US11882700B2

公开(公告)日：2024-01-23

申请号：US17188575

申请日：2021-03-01

Applicant: KIOXIA CORPORATION

Inventor： Yasuhito Yoshimizu ,  Hiroshi Nakaki

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/00 ,  H01L25/18 ,  H01L25/065 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor storage device includes first and second stacks, and first to fourth semiconductor layers. The first stack includes first conductive layers and first insulating layers alternately stacked in a first direction. The first semiconductor layer extends through the first stack. The second semiconductor layer extends in a second direction above the first stack and connected to the first semiconductor layer. The second stack includes second conductive layers and second insulating layers alternately stacked in the first direction. The first and second stacks are arranged in a third direction. The third semiconductor layer extends through the second stack. The fourth semiconductor layer extends in the second direction above the second stack and connected to the third semiconductor layer. A third conductive layer is in contact with upper surfaces of the second and fourth semiconductor layers. The second and fourth semiconductor layers are separated from each other in the third direction.

公开(公告)号：US11587944B2

公开(公告)日：2023-02-21

申请号：US17172947

申请日：2021-02-10

Applicant: KIOXIA CORPORATION

Inventor： Yasuhito Yoshimizu

IPC: H01L27/11578 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11551

Abstract: A semiconductor storage device includes a substrate with a memory cell region and a first region to one side of the memory cell region. A first memory cell layer is on the substrate. A second memory cell layer is between the first memory cell layer and the substrate. A plurality of first conductive layers are stacked on each other in the first memory cell layer. A plurality of second conductive layers are stacked on each other in the second memory cell layer. A plurality of first contacts are above the first region of the substrate, extending through second conductive layer from the substrate to the first memory cell layer. The contacts are electrically insulated from the second conductive layers and electrically connected to ends of the first conductive layers in the first region.

公开(公告)号：US11545437B2

公开(公告)日：2023-01-03

申请号：US17004345

申请日：2020-08-27

Applicant: Kioxia Corporation

Inventor： Takashi Watanabe ,  Yasuhito Yoshimizu

IPC: H01L27/11548 ,  H01L27/11575 ,  H01L23/538 ,  H01L27/11556 ,  G11C5/02 ,  H01L21/768 ,  H01L27/11582

Abstract: A semiconductor device according to one embodiment includes a substrate, a stacked body including conductive layers and insulating layers alternately stacked on the substrate, and first contact plugs individually connected to the conductive layers on an end of the stacked body. The semiconductor device includes, on the substrate, a lower layer three-dimensional structure including any of a lower layer inclined structure continuously inclined upward with respect to a flat surface of the substrate, a lower layer stepped structure inclined upward in a stepwise manner with respect to the flat surface, and a lower layer composite stepped structure in which planes parallel to the flat surface and slopes inclined upward with respect to the flat surface are alternately continuous. At least some of terrace regions being connection regions to the first contact plugs on top surfaces of the conductive layers are located on the lower layer three-dimensional structure.

公开(公告)号：US11422712B2

公开(公告)日：2022-08-23

申请号：US17121024

申请日：2020-12-14

Applicant: Kioxia Corporation

Inventor： Yasuhito Yoshimizu ,  Takashi Fukushima ,  Tatsuro Hitomi ,  Arata Inoue ,  Masayuki Miura ,  Shinichi Kanno ,  Toshio Fujisawa ,  Keisuke Nakatsuka ,  Tomoya Sanuki

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/02

Abstract: According to one embodiment, a storage device includes a stage on which a semiconductor wafer can be mounted, wherein data is capable of being read from the semiconductor wafer or data is capable of being written to the semiconductor wafer. The storage device further includes a plurality of probe pins for reading or writing data, and a controller connected the probe pins. The semiconductor wafer includes electrodes connectable to the probe pins, a first memory area that can store user data, and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information. The controller is capable of reading the identification information and the check code from the second memory area.

公开(公告)号：US12190966B2

公开(公告)日：2025-01-07

申请号：US17899447

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Tomoya Sanuki ,  Hitomi Tanaka ,  Tatsuro Hitomi ,  Yasuhito Yoshimizu ,  Masayuki Miura ,  Yoshihiro Ohba

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  H10B43/00

Abstract: A method of processing a memory system that includes a substrate with a connector and a semiconductor memory chip connected to the connector is provided. The method includes detaching the semiconductor memory chip from the connector, performing an annealing process with respect to the semiconductor memory chip detached from the connector, and after the annealing process, attaching the semiconductor memory chip to the connector on the substrate.