公开(公告)号：US12010837B2

公开(公告)日：2024-06-11

申请号：US17886164

申请日：2022-08-11

Applicant: Kioxia Corporation

Inventor： Yusuke Shima

IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/67 ,  H01L21/768 ,  H01L29/04 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/67075 ,  H01L21/76876 ,  H01L29/04 ,  H10B43/27

Abstract: A semiconductor memory device includes a first region where a plurality of conductive layers, a plurality of insulating layers, a semiconductor layer, and a gate insulating layer are formed and a second region different from the first region above a substrate. The plurality of conductive layers include a plurality of first conductive layers and a plurality of second conductive layers. The semiconductor memory device includes a plurality of first films different from the first conductive layers disposed in same layers as the plurality of first conductive layers in the second region and a plurality of second films different from the second conductive layers and the first films disposed in same layers as the plurality of second conductive layers in the second region.

公开(公告)号：US11456309B2

公开(公告)日：2022-09-27

申请号：US16807625

申请日：2020-03-03

Applicant: Kioxia Corporation

Inventor： Yusuke Shima

IPC: H01L27/11556 ,  G11C5/06 ,  G11C5/02 ,  H01L29/04 ,  H01L21/67 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/3065 ,  H01L27/11582

Abstract: A semiconductor memory device includes a first region where a plurality of conductive layers, a plurality of insulating layers, a semiconductor layer, and a gate insulating layer are formed and a second region different from the first region above a substrate. The plurality of conductive layers include a plurality of first conductive layers and a plurality of second conductive layers. The semiconductor memory device includes a plurality of first films different from the first conductive layers disposed in same layers as the plurality of first conductive layers in the second region and a plurality of second films different from the second conductive layers and the first films disposed in same layers as the plurality of second conductive layers in the second region.

公开(公告)号：US20210066330A1

公开(公告)日：2021-03-04

申请号：US16807625

申请日：2020-03-03

Applicant: Kioxia Corporation

Inventor： Yusuke Shima

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/04 ,  G11C5/06 ,  G11C5/02

Abstract: A semiconductor memory device includes a first region where a plurality of conductive layers, a plurality of insulating layers, a semiconductor layer, and a gate insulating layer are formed and a second region different from the first region above a substrate. The plurality of conductive layers include a plurality of first conductive layers and a plurality of second conductive layers. The semiconductor memory device includes a plurality of first films different from the first conductive layers disposed in same layers as the plurality of first conductive layers in the second region and a plurality of second films different from the second conductive layers and the first films disposed in same layers as the plurality of second conductive layers in the second region.

公开(公告)号：US11672112B2

公开(公告)日：2023-06-06

申请号：US16986853

申请日：2020-08-06

Applicant: Kioxia Corporation

Inventor： Genki Kawaguchi ,  Yasuhito Yoshimizu ,  Yusuke Shima

IPC: G11C5/06 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C5/02

CPC classification number: H01L27/11556 ,  G11C5/025 ,  G11C5/06 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor memory device includes: a plurality of first insulating layers; a plurality of first interconnect layers stacked alternately with the first insulating layers; a plurality of second interconnect layers arranged adjacently to the first interconnect layers; and a separation region including a plurality of first portions provided between the first interconnect layers and the second interconnect layers, and a plurality of second portions protruding from an outer periphery of each of the first portions. The second portions are linked to each other. The first interconnect layers and the second interconnect layers are separated from each other by the first portions and the linked second portions.