- 专利标题: Interconnect retimer enhancements
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申请号: US16725954申请日: 2019-12-23
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公开(公告)号: US11675003B2公开(公告)日: 2023-06-13
- 发明人: Daniel S. Froelich , Debendra Das Sharma
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Alliance IP, LLC
- 主分类号: G01R31/317
- IPC分类号: G01R31/317 ; G06F11/22 ; H04B3/46 ; G01R31/3177 ; G01R31/28 ; G01R31/327 ; G06F11/00 ; G06F11/07 ; G06F11/36 ; G06F13/16 ; H01L21/66
摘要:
A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.
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