Invention Grant
- Patent Title: FeFET transistor
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Application No.: US17323545Application Date: 2021-05-18
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Publication No.: US11677024B2Publication Date: 2023-06-13
- Inventor: Mickael Gros-Jean , Julien Ferrand
- Applicant: STMicroelectronics (Crolles 2) SAS
- Applicant Address: FR Crolles
- Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee Address: FR Crolles
- Agency: Crowe & Dunlevy
- Priority: FR 70707 2018.06.15
- The original application number of the division: US16437067 2019.06.11
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/28 ; H01L27/07 ; H01L29/51 ; H01L29/66

Abstract:
A method for manufacturing first and second transistors on a semiconductor substrate includes: depositing an interface layer on the semiconductor substrate; depositing a gate insulator layer on the interface layer; depositing a first ferroelectric layer on the gate insulator layer over a first region for the first transistor; depositing a metal gate layer on the gate insulator layer over a second region for the second transistor and on the first ferroelectric layer over the first region for the first transistor; and patterning the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer to form a first gate stack for the first transistor which includes the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer and a second gate stack for the second transistor which includes the metal gate layer, gate insulator layer and interface layer.
Public/Granted literature
- US20210280721A1 FeFET TRANSISTOR Public/Granted day:2021-09-09
Information query
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