Invention Grant
- Patent Title: Semiconductor memory device and memory system
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Application No.: US17561545Application Date: 2021-12-23
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Publication No.: US11688458B2Publication Date: 2023-06-27
- Inventor: Noboru Shibata , Tokumasa Hara
- Applicant: Kioxia Corporation
- Applicant Address: JP Tokyo
- Assignee: Kioxia Corporation
- Current Assignee: Kioxia Corporation
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz & Volek PC
- Priority: JP 17029095 2017.02.20
- The original application number of the division: US15702476 2017.09.12
- Main IPC: G11C11/56
- IPC: G11C11/56 ; G11C16/32 ; G11C16/08 ; G11C16/26 ; G11C16/04 ; G11C16/10 ; G11C16/34 ; G06F13/16

Abstract:
A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.
Public/Granted literature
- US20220115064A1 SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM Public/Granted day:2022-04-14
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