The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an isolation structure arranged within a substrate. The isolation structure has one or more surfaces defining one or more trenches that are recessed below an uppermost surface of the isolation structure and that are disposed along opposing sides of an active region of the substrate. A conductive gate is arranged over the substrate between a source region and a drain region. The conductive gate extends into the one or more trenches disposed along opposing sides of the active region of the substrate. The conductive gate has an upper surface that continuously extends past opposing sides of the one or more trenches.