公开(公告)号：US10937879B2

公开(公告)日：2021-03-02

申请号：US16195680

申请日：2018-11-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Meng-Han Lin ,  Wei-Cheng Wu ,  Te-Hsin Chiu

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/792 ,  H01L21/02 ,  H01L27/11573 ,  H01L21/28 ,  H01L27/1157

摘要： A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, and a dielectric structure. The semiconductor substrate has a drain region, a source region, and a channel region between the drain region and the source region. The control gate is over the channel region of the semiconductor substrate. The select gate is over the channel region of the semiconductor substrate and separated from the control gate. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part.

公开(公告)号：US10510855B2

公开(公告)日：2019-12-17

申请号：US15989606

申请日：2018-05-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC分类号： H01L29/00 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/28

摘要： The present disclosure, in some embodiments, relates to a transistor device within an active area having a shape configured to reduce a susceptibility of the transistor device to performance degradation (e.g., the kink effect) caused by divots in an adjacent isolation structure. The transistor device has a substrate including interior surfaces defining a trench within an upper surface of the substrate. One or more dielectric materials are arranged within the trench. The one or more dielectric materials define an opening exposing the upper surface of the substrate. The opening has a source opening over a source region within the substrate, a drain opening over a drain region within the substrate, and a channel opening between the source opening and the drain opening. The source opening and the drain opening have widths smaller than the channel opening. A gate structure extends over the opening between the source and drain regions.

公开(公告)号：US10468410B2

公开(公告)日：2019-11-05

申请号：US15989648

申请日：2018-05-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC分类号： H01L21/00 ,  H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/40

摘要： In some embodiments, the present disclosure, relates to an integrated chip. The integrated chip has an isolation structure arranged within a substrate. The isolation structure has interior surfaces defining one or more divots recessed below an uppermost surface of the isolation structure and sidewalls defining an opening exposing the substrate. A source region is disposed within the opening. A drain region is also disposed within the opening and is separated from the source region by a channel region along a first direction. A gate structure extends over the channel region. The gate structure includes a first gate electrode region having a first composition of one or more materials and a second gate electrode region disposed over the one or more divots and having a second composition of one or more materials different than the first composition of one or more materials.

公开(公告)号：US11923427B2

公开(公告)日：2024-03-05

申请号：US17185915

申请日：2021-02-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Meng-Han Lin ,  Wei-Cheng Wu ,  Te-Hsin Chiu

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/792 ,  H10B43/35 ,  H10B43/40

CPC分类号： H01L29/42368 ,  H01L21/02244 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792 ,  H10B43/35 ,  H10B43/40

摘要： A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, and a dielectric structure. The semiconductor substrate has a drain region, a source region, and a channel region between the drain region and the source region. The control gate is over the channel region of the semiconductor substrate. The select gate is over the channel region of the semiconductor substrate and separated from the control gate. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part.

公开(公告)号：US11211388B2

公开(公告)日：2021-12-28

申请号：US16022702

申请日：2018-06-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei-Cheng Wu ,  Li-Feng Teng ,  Chien-Hung Chang

IPC分类号： H01L27/112 ,  H01L29/06 ,  H01L23/00 ,  H01L21/765 ,  H01L29/40 ,  H01L29/66 ,  H01L27/11534 ,  H01L21/762 ,  H01L27/11524 ,  H01L27/11546 ,  H01L21/28

摘要： A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

公开(公告)号：US10784270B2

公开(公告)日：2020-09-22

申请号：US16051721

申请日：2018-08-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC分类号： H01L27/11536 ,  H01L29/788 ,  H01L29/423 ,  H01L29/49 ,  H01L29/08 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/027 ,  H01L27/11521

摘要： Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A sidewall spacer is disposed along a sidewall surface of the logic devices, but not disposed along a sidewall surface of the memory cell structures. Thus, the inter-layer dielectric (ILD) fill-in window between adjacent memory cell structures is enlarged, compared to the approaches where the sidewall spacer is concurrently formed in both memory region and the logic region. Thereby, voids formation would be reduced or eliminated, and device quality would be improved.

公开(公告)号：US10665595B2

公开(公告)日：2020-05-26

申请号：US15903770

申请日：2018-02-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Te-Hsin Chiu ,  Meng-Han Lin ,  Wei Cheng Wu

IPC分类号： G06F17/50 ,  H01L27/11 ,  H01L23/528 ,  G11C29/50 ,  G11C29/08 ,  G11C29/04 ,  G11C29/12 ,  G06F30/39 ,  G06F30/398

摘要： In the present disclosure, it has been appreciated that memory structures, such as static random access memory (SRAM) structures, have feature densities that are extremely high. While this is beneficial in allowing the memory structures to store large amounts of data in a small chip footprint, it is potentially detrimental in that it makes the memory structures more susceptible to leakage current than the other areas of the chip. Accordingly, the present disclosure provides pseudo memory structures which are similar in terms of layout spacing to actual memory structures. However, rather than being used as actual memory structures that store data during operation, these pseudo memory structures are used to characterize leakage current in the design of the IC and/or to characterize the fabrication process used to manufacture the IC.

公开(公告)号：US20200013790A1

公开(公告)日：2020-01-09

申请号：US16574247

申请日：2019-09-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC分类号： H01L27/11536 ,  H01L21/28 ,  H01L21/768 ,  H01L29/788 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/66 ,  H01L21/762 ,  H01L21/3105 ,  H01L29/49 ,  H01L29/08 ,  H01L29/423 ,  H01L27/11521 ,  H01L21/321

摘要： Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A sidewall spacer is disposed along a sidewall surface of the logic devices, but not disposed along a sidewall surface of the memory cell structures. Thus, the inter-layer dielectric (ILD) fill-in window between adjacent memory cell structures is enlarged, compared to the approaches where the sidewall spacer is concurrently formed in both memory region and the logic region. Thereby, voids formation would be reduced or eliminated, and device quality would be improved.

公开(公告)号：US20200006466A1

公开(公告)日：2020-01-02

申请号：US16273260

申请日：2019-02-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu ,  Te-An Chen

IPC分类号： H01L49/02 ,  H01L27/06 ,  H01L21/8234

摘要： A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a substrate having isolation structures therein and a capacitor structure located on a top surface of the isolation structure. The capacitor structure comprises a semiconductor material pattern and an insulator pattern inlaid in the semiconductor material pattern. The semiconductor material pattern and the insulator pattern are located at a same horizontal level on the isolation structure.

公开(公告)号：US20240194734A1

公开(公告)日：2024-06-13

申请号：US18584387

申请日：2024-02-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Wei PENG ,  Te-Hsin Chiu ,  Jiann-Tyng TZENG

IPC分类号： H01L29/06 ,  H01L23/522 ,  H01L25/11 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/0673 ,  H01L23/5226 ,  H01L25/115 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/78618

摘要： A semiconductor device including vertical transistors with a back side power structure, and methods of making the same are described. In one example, a described semiconductor structure includes: a gate structure including a gate pad and a gate contact on the gate pad; a first source region disposed below the gate pad; a first drain region disposed on the gate pad, wherein the first source region, the first drain region and the gate structure form a first transistor; a second source region disposed below the gate pad; a second drain region disposed on the gate pad, wherein the second source region, the second drain region and the gate structure form a second transistor; and at least one metal line that is below the first source region and the second source region, and is electrically connected to at least one power supply.