Invention Grant
- Patent Title: Error avoidance based on voltage distribution parameters
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Application No.: US17164636Application Date: 2021-02-01
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Publication No.: US11705193B2Publication Date: 2023-07-18
- Inventor: Shane Nowell , Steven Michael Kientz , Michael Sheperek , Mustafa N Kaynak , Kishore Kumar Muchherla , Larry J Koudele , Bruce A Liikanen
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C11/56 ; G11C16/10 ; G11C16/26 ; G11C16/30

Abstract:
A method can include receiving a request to read data from a memory cell of a memory device coupled with the processing device, determining a voltage distribution parameter value associated with the memory cell, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the determined set of read levels corresponds to a respective voltage distribution of the memory cell, and reading, using the determined set of read levels, data from the memory cell. The voltage distribution parameter value can be determined by identifying a particular voltage distribution of the memory cell by sampling the memory cell at a plurality of voltage levels, and determining the voltage distribution parameter value based on the particular voltage distribution. The voltage distribution parameter value can be a voltage value that is included in the particular voltage distribution.
Public/Granted literature
- US20220246207A1 ERROR AVOIDANCE BASED ON VOLTAGE DISTRIBUTION PARAMETERS Public/Granted day:2022-08-04
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