公开(公告)号：US12125539B2

公开(公告)日：2024-10-22

申请号：US17861467

申请日：2022-07-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Bruce A. Liikanen ,  Michael Sheperek ,  Larry J. Koudele

IPC: G11C16/10 ,  G06F3/06 ,  G11C16/04

CPC classification number: G11C16/10 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483

Abstract: A processing device determines a measured bit error count (BEC) value corresponding to a read sample offset operation executed on a first programming voltage distribution of memory cells of a plurality of programming voltage distributions of a memory sub-system. The measured BEC value of the portion of the programming voltage distribution is compared to a threshold BEC value to generate a comparison result. In view of the comparison result, an adjusted program start voltage level is determined by adjusting a default program voltage level of a programming process. The programming process including a series of programming pulses is executed, where the adjusted program start voltage level is set as a starting voltage level of a first programming pulse of the series of programming pulses.

公开(公告)号：US20240111445A1

公开(公告)日：2024-04-04

申请号：US18526634

申请日：2023-12-01

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Vamsi Pavan Rayaprolu ,  Bruce A. Liikanen ,  Peter Feeley ,  Larry J. Koudele ,  Shane Nowell ,  Steven Michael Kientz

IPC: G06F3/06 ,  G06F12/10 ,  G11C16/26

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/10 ,  G11C16/26 ,  G11C16/0483

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.

公开(公告)号：US11768619B2

公开(公告)日：2023-09-26

申请号：US17868124

申请日：2022-07-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Sheperek ,  Kishore Kumar Muchherla ,  Shane Nowell

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0679

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a first block family comprising a first set of blocks, wherein the first block family comprises a plurality of blocks that have been programmed within at least one of a specified time window or a specified temperature window; identify a second block family comprising a second set of blocks; and responsive to a determining that a threshold criterion is satisfied, combine the first block family and the second block family by appending, to first block family metadata of the first block family, a record referencing the second set of blocks.

公开(公告)号：US11755478B2

公开(公告)日：2023-09-12

申请号：US17667326

申请日：2022-02-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Mustafa N. Kaynak ,  Shane Nowell

IPC: G06F12/0802 ,  G06F12/06 ,  G11C16/10

CPC classification number: G06F12/0802 ,  G06F12/06 ,  G11C16/107

Abstract: A set of two or more block families associated with a bin boundary of a first voltage bin is identified. A determination of at least a first voltage for a first block family of the plurality of block families and a second voltage for a second block family of the plurality of block families based on values of a data state metric for each of the plurality of block families. In response to a determination that a difference between the first voltage and the second voltage satisfies a block family combination criterion, the second block family is merged with the first block family.

公开(公告)号：US11733929B2

公开(公告)日：2023-08-22

申请号：US17819857

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Steve Kientz

IPC: G06F3/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/04

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G11C16/26 ,  G11C16/0483

Abstract: A memory device includes a processing device configured to iteratively update a center read level according to a first step size after reading a subset of memory cells according to a set of read levels including the center read level; track an update direction for the processing device to use when iteratively updating the center read level, wherein the update direction corresponds to an increase or a decrease in the center read level; detect a change condition based on updating the center read level according to the first step size; and iteratively update the center read level according to a second step size based on detection of the change condition.

公开(公告)号：US11733896B2

公开(公告)日：2023-08-22

申请号：US17744563

申请日：2022-05-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vamsi Pavan Rayaprolu ,  Shane Nowell ,  Michael Sheperek

IPC: G06F3/06 ,  G11C16/04

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483

Abstract: A system can include a memory device and a processing device to perform operations that include performing, at a first frequency, a calibration scan, where the calibration scan includes calibrating block family-to-bin associations for one or more younger voltage bins based on first measurement data determined by the calibration scan, and calibrating block family-to-bin associations for one or more older voltage bins based on second measurement data provided by a media management scan, where the media management scan is performed at a second frequency, such that the second frequency is lower than the first frequency, each of the younger voltage bins satisfies a first age threshold criterion, and each of the older voltage bins satisfies a second age threshold criterion.

公开(公告)号：US11705193B2

公开(公告)日：2023-07-18

申请号：US17164636

申请日：2021-02-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shane Nowell ,  Steven Michael Kientz ,  Michael Sheperek ,  Mustafa N Kaynak ,  Kishore Kumar Muchherla ,  Larry J Koudele ,  Bruce A Liikanen

IPC: G11C11/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: A method can include receiving a request to read data from a memory cell of a memory device coupled with the processing device, determining a voltage distribution parameter value associated with the memory cell, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the determined set of read levels corresponds to a respective voltage distribution of the memory cell, and reading, using the determined set of read levels, data from the memory cell. The voltage distribution parameter value can be determined by identifying a particular voltage distribution of the memory cell by sampling the memory cell at a plurality of voltage levels, and determining the voltage distribution parameter value based on the particular voltage distribution. The voltage distribution parameter value can be a voltage value that is included in the particular voltage distribution.

公开(公告)号：US20230153003A1

公开(公告)日：2023-05-18

申请号：US18098439

申请日：2023-01-18

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen ,  Steven Michael Kientz ,  Kishore Kumar Muchherla

IPC: G06F3/06 ,  G01K3/04 ,  G06F1/324 ,  G06F1/3228

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0659 ,  G01K3/04 ,  G06F1/324 ,  G06F1/3228 ,  G06F3/0679

Abstract: A system includes a memory device and a processing device to initialize a block family associated with the memory device and a timer at initialization of the block family. The processing device further stores, in non-volatile memory of the memory device, a value of the timer before powering down the system while the block family is still open. The processing device further detects a power on of the system and measures a data state metric associated with one or more memory cell of a page of the memory device that is associated with the block family. The processing device further compares a level of the data state metric to a temporal voltage shift function to estimate a time after program value of the page and increments the value of the timer, restored from the non-volatile memory, based on the time after program value.

公开(公告)号：US11651828B2

公开(公告)日：2023-05-16

申请号：US17379868

申请日：2021-07-19

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen

IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5622 ,  G11C2216/16

Abstract: Described herein are embodiments related to first-pass dynamic program targeting (DPT) operations on memory cells of memory systems. A method includes determining that a first programming pass of a programming operation has been performed on a memory cell of the memory component, and performing a dynamic program targeting (DPT) operation on the memory cell to calibrate a first program-verify (PV) target value that results in an adjustment to a placement of a first first-pass programming distribution and a second PV target value that results in an adjustment to a placement of a second first-pass programming distribution before a second programming pass of the programming operation is performed on the memory cell.

公开(公告)号：US11636913B2

公开(公告)日：2023-04-25

申请号：US17301350

申请日：2021-03-31

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Bruce A. Liikanen ,  Steven Michael Kientz

IPC: G11C16/10 ,  G11C29/42 ,  G11C29/44 ,  G11C16/16 ,  G11C16/26 ,  G11C29/12

Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, responsive to detecting a triggering event, selecting a family of memory blocks of the memory device, the selected family being associated with a set of bins, each bin associated with a plurality of read voltage offsets to be applied to base read voltages during read operations. The operations performed by the processing device further include calibration operations to determine data state metric values characterizing application of read voltage offsets of various bins. The operations performed by the processing device further include identifying, based on the determined data state metrics, a target bin and associating the selected family with the target bin.