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公开(公告)号：US20220319589A1
公开(公告)日：2022-10-06
申请号：US17217772
申请日：2021-03-30
发明人： Shane Nowell , Steven Michael Kientz , Michael Sheperek , Mustafa N Kaynak , Kishore Kumar Muchherla , Larry J Koudele , Bruce A Liikanen
摘要： A method can include receiving a request to read data from a block of a memory device coupled with a processing device, determining, using a data structure mapping block identifiers to corresponding voltage distribution parameter values, a voltage distribution parameter value associated with the block of the memory device, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block, and reading, using the determined set of read levels, data from the block of the memory device.
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公开(公告)号：US11443830B1
公开(公告)日：2022-09-13
申请号：US17217780
申请日：2021-03-30
摘要： A method can include receiving a request to read data from a block of a memory device coupled with a processing device, determining, using a first data structure mapping block identifiers to corresponding block family identifiers, a block family associated with the block of the memory device, determining, using a second data structure mapping block family identifiers to corresponding voltage distribution parameter values, a voltage distribution parameter value associated with the block family, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block of the memory device, and reading, using the determined set of read levels, data from the block of the memory device.
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公开(公告)号：US11928347B2
公开(公告)日：2024-03-12
申请号：US18114967
申请日：2023-02-27
发明人： Kishore Kumar Muchherla , Mustafa N Kaynak , Peter Feeley , Sampath K Ratnam , Shane Nowell , Sivagnanam Parthasarathy , Karl D Schuh , Jiangang Wu
CPC分类号： G06F3/0632 , G06F3/0604 , G06F3/064 , G06F3/0679 , G11C16/26
摘要： A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; identify, based on scanning of a first block at a first location of the plurality of sorted block, a first voltage bin associated with the first block; identify, based on scanning of a second block at a second location of the plurality of sorted blocks, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block that is located between the first location of the plurality of sorted blocks and the second location of the plurality of sorted blocks.
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公开(公告)号：US20230282293A1
公开(公告)日：2023-09-07
申请号：US18110008
申请日：2023-02-15
发明人： Kishore Kumar Muchherla , Mustafa N Kaynak , Sampath K Ratnam , Shane Nowell , Peter Feeley , Sivagnanam Parthasarathy
CPC分类号： G11C16/3404 , G11C16/30 , G11C16/102 , G11C16/32 , G11C16/26
摘要： A processing device of a memory sub-system is configured to identify a read level of a plurality of read levels associated with a voltage bin of a plurality of voltage bins of a memory device; assign a first threshold voltage offset to the read level of the voltage bin; assign a second threshold voltage offset to the read level of the voltage bin; perform, on block associated with the read level, a first operation of a first operation type using the first threshold voltage offset; and perform, on the blocks associated with the read level, a second operation of a second operation type using the second threshold voltage offset.
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公开(公告)号：US11587627B2
公开(公告)日：2023-02-21
申请号：US17233320
申请日：2021-04-16
发明人： Kishore Kumar Muchherla , Mustafa N Kaynak , Sampath K Ratnam , Shane Nowell , Peter Feeley , Sivagnanam Parthasarathy
摘要： A processing device of a memory sub-system is configured to identify a read level of a plurality of read levels associated with a voltage bin of a plurality of voltage bins of a memory device; assign a first threshold voltage offset to the read level of the voltage bin; assign a second threshold voltage offset to the read level of the voltage bin; perform, on block associated with the read level, a first operation of a first operation type using the first threshold voltage offset; and perform, on the blocks associated with the read level, a second operation of a second operation type using the second threshold voltage offset.
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公开(公告)号：US11915776B2
公开(公告)日：2024-02-27
申请号：US17943123
申请日：2022-09-12
CPC分类号： G11C29/56008 , G11C16/26
摘要： A method can include receiving a request to read data from a block of a memory device, identifying a block family associated with the block of the memory device, identifying a voltage distribution parameter value associated with the block family, wherein the voltage distribution parameter value reflects an aggregate value of a corresponding voltage distribution associated with a plurality of memory cells of the block family, and determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block of the memory device. The block family can be identified using a data structure that maps block identifiers to corresponding block family identifiers. The voltage distribution parameter value can be identified using a data structure that maps block family identifiers to corresponding voltage parameter values.
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公开(公告)号：US11823748B2
公开(公告)日：2023-11-21
申请号：US17820792
申请日：2022-08-18
发明人： Kishore Kumar Muchherla , Karl Schuh , Mustafa N Kaynak , Xiangang Luo , Shane Nowell , Devin Batutis , Sivagnanam Parthasarathy , Sampath Ratnam , Jiangang Wu , Peter Feeley
CPC分类号： G11C16/30 , G11C7/04 , G11C16/102 , G11C16/26 , G11C16/32 , G11C16/34 , G11C16/3427
摘要： A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.
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公开(公告)号：US11735254B2
公开(公告)日：2023-08-22
申请号：US17217772
申请日：2021-03-30
发明人： Shane Nowell , Steven Michael Kientz , Michael Sheperek , Mustafa N Kaynak , Kishore Kumar Muchherla , Larry J Koudele , Bruce A Liikanen
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/10 , G11C16/26 , G11C16/30
摘要： A method can include receiving a request to read data from a block of a memory device coupled with a processing device, determining, using a data structure mapping block identifiers to corresponding voltage distribution parameter values, a voltage distribution parameter value associated with the block of the memory device, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block, and reading, using the determined set of read levels, data from the block of the memory device.
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9.发明授权公开(公告)号：US11429309B2
公开(公告)日：2022-08-30
申请号：US16930064
申请日：2020-07-15
发明人： Mustafa N Kaynak , Sampath K Ratnam , Zixiang Loh , Nagendra Prasad Ganesh Rao , Larry K Koudele , Vamsi Pavan Rayaprolu , Patrick R Khayat , Shane Nowell
摘要： A processing device, operatively coupled with a memory device, is configured to identify a temperature related to a memory device of a plurality of memory devices; to determine, whether the temperature satisfies a threshold temperature condition; responsive to detecting that the temperature related to the memory device satisfies the threshold temperature condition, to identify an entry associated with the memory device from a plurality of entries in a data structure, wherein each entry of the plurality of entries corresponds to one of the plurality of memory devices; to determine a parameter value associated with the memory device from the entry, wherein the parameter value is for a programming operation to store data at the memory device; to adjust the parameter value associated with the memory device to generate an adjusted parameter value; and to store the adjusted parameter value in the entry of the data structure.
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10.发明授权公开(公告)号：US11847317B2
公开(公告)日：2023-12-19
申请号：US17850956
申请日：2022-06-27
发明人： Shane Nowell , Mustafa N Kaynak
CPC分类号： G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C16/26 , G11C16/0483
摘要： A processing device of a memory sub-system is configured to select, during a first period of time of a plurality of predetermined periods of time, a first voltage bin of a plurality of voltage bins associated with a memory device; perform, during a second period of time, a read operation of a block of the memory device, using a first set of read level offsets associated with the first voltage bin; determine a trigger metric associated with the first set of read level offsets; and responsive to determining that the trigger metric satisfies a predefined condition, performing a second read operation, during a third period of time, using the first set of read level offsets associated with the first voltage bin.
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