Invention Grant
- Patent Title: Memory array staircase structure
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Application No.: US17814341Application Date: 2022-07-22
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Publication No.: US11776602B2Publication Date: 2023-10-03
- Inventor: Meng-Han Lin , Han-Jong Chia , Sheng-Chen Wang , Feng-Cheng Yang , Yu-Ming Lin , Chung-Te Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: G11C8/14
- IPC: G11C8/14 ; H01L21/822 ; H10B51/20 ; H10B99/00

Abstract:
Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.
Public/Granted literature
- US20220366952A1 Memory Array Staircase Structure Public/Granted day:2022-11-17
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