Invention Grant
- Patent Title: Single chip multi-die architecture having safety-compliant cross-monitoring capability
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Application No.: US16439407Application Date: 2019-06-12
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Publication No.: US11841776B2Publication Date: 2023-12-12
- Inventor: Nabajit Deka , Riccardo Mariani , Asad Azam , Roger May , Prashanth Gadila
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/16 ; G05B9/02 ; G06F11/30 ; G06F13/12 ; G06F11/07

Abstract:
Methods, systems and apparatuses may provide for technology that includes a chip having a first die including a first processing logic to execute a first application instance and generate a first output of the first application instance, and a second processing logic to execute a second application instance and generate a second output of the second application instance. The chip may also include a second die coupled to the first die, wherein the second die includes a safety monitor detect a condition associated with one or more of an error in the first output, an error in the second output, or a discrepancy between the first output and the second output. The safety monitor may also initiate a transition of the chip into a safe state in response to the condition.
Public/Granted literature
- US20190294125A1 SINGLE CHIP MULTI-DIE ARCHITECTURE HAVING SAFETY-COMPLIANT CROSS-MONITORING CAPABILITY Public/Granted day:2019-09-26
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