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公开(公告)号：US20190051370A1
公开(公告)日：2019-02-14
申请号：US16155606
申请日：2018-10-09
申请人： Intel Corporation
摘要： The disclosed embodiments relate to method, apparatus and system for testing memory circuitry and diagnostic components designed to test the memory circuitry. The memory may be tested regularly using Memory Built-In Self-Test (MBIST) to detect memory failure. Error Correction Code (ECC)/Parity is implemented for SRAM/Register Files/ROM memory structures to protect against transient and permanent faults during runtime. ECC/Parity encoder and decoder logic detect failure on both data and address buses and are intended to catch soft error or structural fault in address decoding logic in SRAM Controller, where data may be read/written from/to different locations due to faults. ECC/parity logic on the memory structures are subject to failures. In certain exemplary embodiments, an array test controller is used to generate and transmit error vectors to thereby determine faulty diagnostic components. The test vectors may be generated randomly to test the diagnostic components during run-time for in-field testing.
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公开(公告)号：US11113402B2
公开(公告)日：2021-09-07
申请号：US16370566
申请日：2019-03-29
申请人： Intel Corporation
发明人： Mikal Hunsaker , Mark Feuerstraeter , Asad Azam , Zhenyu Zhu , Navtej Singh
IPC分类号： G06F9/00 , G06F15/177 , G06F21/57 , G05B9/02 , G05B19/042
摘要： Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having a root of trust and an embedded controller to conduct functional safety operations and non-functional safety operations with respect to the SoC. The technology may also include an enhanced serial peripheral interface (eSPI) coupled to the SoC and the embedded controller, wherein the eSPI is to tunnel communications associated with the functional safety operations between the embedded controller and the root of trust.
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3.发明申请公开(公告)号：US20210003629A1
公开(公告)日：2021-01-07
申请号：US17031107
申请日：2020-09-24
申请人： Intel Corporation
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/3185 , G11C29/32 , G11C29/46 , G11C29/36 , G11C29/08
摘要： An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode.
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公开(公告)号：US10853289B2
公开(公告)日：2020-12-01
申请号：US16221962
申请日：2018-12-17
申请人： Intel Corporation
IPC分类号： G06F13/36 , G06F13/364 , H04L12/801 , H04L12/835 , G06F13/24 , G06F13/16 , G06F13/42 , H04L5/16
摘要： In one embodiment, a host controller includes: a first credit tracker comprising at least one credit counter to maintain credit information for a first device; and a first credit handler to send a command code having a first predetermined value to indicate a credit request to request credit information from the first device, where the first credit tracker is to update the at least one credit counter based on receipt of an in-band interrupt from the first device having the credit information. Other embodiments are described and claimed.
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公开(公告)号：US10745023B2
公开(公告)日：2020-08-18
申请号：US16021911
申请日：2018-06-28
申请人： INTEL CORPORATION
摘要： A voltage monitoring framework is proposed to predict, report, and correct actions for performance impacting voltage droop due to power supplies in a system-on-a-chip. Both the amplitude and duration of the voltage droop are monitored. By predicting serious voltage droops early, power supplies cross check against each other to avoid catastrophic error, thus ensuring that integrated circuits making up the system-on-a-chip will maintain functional reliability.
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6.发明申请公开(公告)号：US20190121765A1
公开(公告)日：2019-04-25
申请号：US16221962
申请日：2018-12-17
申请人： Intel Corporation
IPC分类号： G06F13/364 , H04L12/801 , H04L12/835 , G06F13/24 , G06F13/16 , G06F13/42 , H04L5/16
摘要： In one embodiment, a host controller includes: a first credit tracker comprising at least one credit counter to maintain credit information for a first device; and a first credit handler to send a command code having a first predetermined value to indicate a credit request to request credit information from the first device, where the first credit tracker is to update the at least one credit counter based on receipt of an in-band interrupt from the first device having the credit information. Other embodiments are described and claimed.
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7.发明申请公开(公告)号：US20190049513A1
公开(公告)日：2019-02-14
申请号：US16017764
申请日：2018-06-25
申请人： Intel Corporation
发明人： Asad Azam , Amit K. Srivastava , Enrico Carrieri , Rajesh Bhaskar
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/3177
摘要： An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode.
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公开(公告)号：US11073554B2
公开(公告)日：2021-07-27
申请号：US16586731
申请日：2019-09-27
申请人： Intel Corporation
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/317 , G06F11/10
摘要： Apparatuses of a scan controller include memory and circuitry, where the circuitry is configured to respond to a first signal by sending a second signal to isolate state retention elements from non-state retention elements in a scan chain of power gating circuitry and cycling through the scan chain while obtaining state retention data from the state retention elements during each cycle. The circuitry may be further configured to determine a first error detection code from the state retention data and store the error detection code in the memory. The circuitry may be configured to determine a second error detection code in response to another signal and compare the first error detection code with the second error detection code. The circuitry may be configured to send a signal indicating that the state retention data is corrupted if the first error detection code does not match the second error detection code.
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公开(公告)号：US10942880B2
公开(公告)日：2021-03-09
申请号：US16236471
申请日：2018-12-29
申请人： Intel Corporation
发明人： Amit Kumar Srivastava , Asad Azam
摘要： An integrated circuit for monitoring components of the integrated circuit, comprising: a resource monitoring circuit configured to: track activity factors for a plurality of components of the integrated circuit; evaluate the activity factors for each of the plurality of components; determine whether an activity factor for a particular component of the plurality of components exceeds a threshold; and transmit, from the resource monitoring circuit, a signal to a software element, causing the software element to deactivate the particular component and activate an alternate component, when the activity factor for the particular component exceeds the threshold and the alternate component is available to substitute for the particular component.
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公开(公告)号：US20210004241A1
公开(公告)日：2021-01-07
申请号：US17025350
申请日：2020-09-18
申请人： Intel Corporation
IPC分类号： G06F9/4401 , G06F9/30 , G06F12/0811
摘要： Embodiments are directed to improving boot process for early display initialization and visualization. An embodiment of a system includes a plurality of processor cores; a cache coupled to the plurality of processor cores; and a controller circuit to: initialize a portion of the cache as static memory for hardware initialization code usage before beginning execution of the hardware initialization code after a power on of the hardware processor; and cause initialization of a display device to be performed using the portion of the cache, the initialization of the display device performed independently of initialization of dynamic memory of the hardware processor.
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