Invention Grant
- Patent Title: Vertical transistor, integrated circuitry, method of forming a vertical transistor, and method of forming integrated circuitry
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Application No.: US17589310Application Date: 2022-01-31
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Publication No.: US11871582B2Publication Date: 2024-01-09
- Inventor: Hung-Wei Liu , Vassil N. Antonov , Ashonita A. Chavan , Darwin Franseda Fan , Jeffery B. Hull , Anish A. Khandekar , Masihhur R. Laskar , Albert Liao , Xue-Feng Lin , Manuj Nahar , Irina V. Vasilyeva
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- The original application number of the division: US17027046 2020.09.21
- Main IPC: H10B53/20
- IPC: H10B53/20 ; H01L29/78 ; H01L29/66 ; H01L29/10 ; H01L21/223 ; H10B51/20 ; H10B51/30 ; H10B53/30

Abstract:
A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.
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