公开(公告)号：US20160351580A1

公开(公告)日：2016-12-01

申请号：US14722824

申请日：2015-05-27

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Darwin Franseda Fan

IPC: H01L27/115 ,  H01L29/49 ,  H01L21/311 ,  H01L29/788 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L29/4916 ,  H01L21/28273 ,  H01L27/11556 ,  H01L29/42324 ,  H01L29/7883

Abstract: Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess.

Abstract translation: 本文一般讨论保护电介质。 在一个或多个实施例中，三维垂直存储器可以包括保护电介质材料。 器件可以包括蚀刻停止材料，蚀刻停止材料上方的第一控制栅极（CG），与第一CG相邻的第一CG凹槽，与第一CG凹槽相邻的沟槽，以及至少部分氧化的多晶硅 蚀刻停止材料的一部分。 至少部分氧化的多晶硅可以在沟槽的侧壁上划线，并且可以使第一CG凹槽成线。

公开(公告)号：US20150140797A1

公开(公告)日：2015-05-21

申请号：US14610755

申请日：2015-01-30

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Darwin Franseda Fan ,  Fatma Arzum Simsek-Ege ,  James Brighten ,  Aurelio Giancarlo Mauri ,  Srikant Jayanti

IPC: H01L27/115 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L29/7887 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7881 ,  H01L29/7889

Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

Abstract translation: 三维存储器单元以及制造和使用存储器单元的方法一般在此讨论。 在一个或多个实施例中，三维垂直存储器可以包括存储器堆栈。 这样的存储器堆可以包括存储器单元和相邻存储单元之间的电介质，每个存储单元包括控制栅极和电荷存储结构。 存储单元还可以包括电荷存储结构和控制栅极之间的阻挡材料，电荷存储结构和阻挡材料具有基本相等的尺寸。

公开(公告)号：US08946807B2

公开(公告)日：2015-02-03

申请号：US13748747

申请日：2013-01-24

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Darwin Franseda Fan ,  Fatma Arzum Simsek-Ege ,  James Brighten ,  Aurelio Giancarlo Mauri ,  Srikant Jayanti

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/7887 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7881 ,  H01L29/7889

Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

Abstract translation: 三维存储器单元以及制造和使用存储器单元的方法一般在此讨论。 在一个或多个实施例中，三维垂直存储器可以包括存储器堆栈。 这样的存储器堆可以包括存储器单元和相邻存储单元之间的电介质，每个存储单元包括控制栅极和电荷存储结构。 存储单元还可以包括电荷存储结构和控制栅极之间的阻挡材料，电荷存储结构和阻挡材料具有基本相等的尺寸。

公开(公告)号：US20240136391A1

公开(公告)日：2024-04-25

申请号：US18047978

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Sanket S. Kelkar ,  Michael Mutch ,  Luca Fumagalli ,  Hisham Abdussamad Abbas ,  Brenda D. Kraus ,  Dojun Kim ,  Christopher W. Petz ,  Darwin Franseda Fan

IPC: H01L49/02 ,  H01G4/008 ,  H01G4/12 ,  H01L27/108

CPC classification number: H01L28/75 ,  H01G4/008 ,  H01G4/1218 ,  H01L27/10814 ,  H01L27/10852

Abstract: A microelectronic device comprises an access device comprising a source region and a drain region spaced from the source region, an insulative material vertically adjacent to the access device, and a capacitor within the insulative material and in electrical communication with the access device. The capacitor comprises a material comprising silicon oxynitride or titanium silicon nitride over surfaces of the insulative material, a first electrode comprising titanium nitride on the material, a dielectric material over the first electrode, and a second electrode on the dielectric material. Related methods of forming the microelectronic device and an electronic system including the microelectronic devices are also described.

公开(公告)号：US20240105766A1

公开(公告)日：2024-03-28

申请号：US18531525

申请日：2023-12-06

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Masihhur R. Laskar ,  Nicholas R. Tapias ,  Darwin Franseda Fan ,  Manuj Nahar

IPC: H01L29/04 ,  H01L29/10

CPC classification number: H01L29/04 ,  H01L29/1033 ,  H10B12/00

Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

公开(公告)号：US11923272B2

公开(公告)日：2024-03-05

申请号：US17721919

申请日：2022-04-15

Applicant: Micron Technology, Inc.

Inventor： Zhuo Chen ,  Irina V. Vasilyeva ,  Darwin Franseda Fan ,  Kamal Kumar Muthukrishnan

IPC: H01L21/48 ,  H01L23/48 ,  H10B12/00 ,  H10B53/10 ,  H10B53/30 ,  H10B53/40

CPC classification number: H01L23/481 ,  H01L21/4814 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/50 ,  H10B53/10 ,  H10B53/30 ,  H10B53/40

Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

公开(公告)号：US20220157837A1

公开(公告)日：2022-05-19

申请号：US17589310

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Vassil N, Antonov ,  Ashonita A. Chavan ,  Darwin Franseda Fan ,  Jeffrey B. Hull ,  Anish A. Khandekar ,  Masihhur R. Laskar ,  Albert Liao ,  Xue-Feng Lin ,  Manuj Nahar ,  Irina V. Vasilyeva

IPC: H01L27/11514 ,  H01L27/11507 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/78 ,  H01L29/66 ,  H01L21/223 ,  H01L29/10

Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

公开(公告)号：US20220093617A1

公开(公告)日：2022-03-24

申请号：US17027046

申请日：2020-09-21

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Vassil N. Antonov ,  Ashonita A. Chavan ,  Darwin Franseda Fan ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Masihhur R. Laskar ,  Albert Liao ,  Xue-Feng Lin ,  Manuj Nahar ,  Irina V. Vasilyeva

IPC: H01L27/11514 ,  H01L27/11507 ,  H01L29/78 ,  H01L21/223 ,  H01L27/11597 ,  H01L27/1159 ,  H01L29/10 ,  H01L29/66

Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

公开(公告)号：US10886130B2

公开(公告)日：2021-01-05

申请号：US16112410

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Darwin Franseda Fan ,  Junting Liu-Norrod ,  Michael Mutch

IPC: H01L21/76 ,  H01L21/20 ,  H01L21/02 ,  C23C16/56 ,  H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L27/108 ,  C23C16/24 ,  C23C16/06 ,  H01L27/24

Abstract: Some embodiments include a method of forming crystalline semiconductor material. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The deposition is conducted at a temperature of less than or equal to 500° C. Some embodiments include a method of forming a transistor. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The semiconductor material includes germanium. The crystalline semiconductor structures are doped to form a configuration having a first portion over a second portion. Insulative material is formed adjacent the second portion. A transistor gate is formed along the insulative material.

公开(公告)号：US20200066513A1

公开(公告)日：2020-02-27

申请号：US16112410

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Darwin Franseda Fan ,  Junting Liu-Norrod ,  Michael Mutch

IPC: H01L21/02 ,  H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L27/108 ,  C23C16/24 ,  C23C16/06 ,  C23C16/56

Abstract: Some embodiments include a method of forming crystalline semiconductor material. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The deposition is conducted at a temperature of less than or equal to 500° C. Some embodiments include a method of forming a transistor. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The semiconductor material includes germanium. The crystalline semiconductor structures are doped to form a configuration having a first portion over a second portion. Insulative material is formed adjacent the second portion. A transistor gate is formed along the insulative material.