公开(公告)号：US11469043B2

公开(公告)日：2022-10-11

申请号：US17183285

申请日：2021-02-23

申请人： Micron Technology, Inc.

发明人： Manuj Nahar ,  Ashonita A. Chavan

IPC分类号： H01L21/02 ,  H01G4/10 ,  H01G4/30 ,  H01L29/66 ,  H01L27/1159 ,  H01L27/11507 ,  H01G4/33 ,  H01L29/78 ,  H01L49/02 ,  H01L21/28 ,  H01L29/51 ,  H01G4/40

摘要： A method used in forming an electronic device comprising conductive material and ferroelectric material comprises forming a composite stack comprising multiple metal oxide-comprising insulator materials. At least one of the metal oxide-comprising insulator materials is between and directly against non-ferroelectric insulating materials. The multiple metal oxide-comprising insulator materials are of different composition from that of immediately-adjacent of the non-ferroelectric insulating materials. The composite stack is subjected to a temperature of at least 200° C. After the subjecting, the composite stack comprises multiple ferroelectric metal oxide-comprising insulator materials at least one of which is between and directly against non-ferroelectric insulating materials. After the subjecting, the composite stack is ferroelectric. Conductive material is formed and that is adjacent the composite stack. Devices are also disclosed.

公开(公告)号：US20220028442A1

公开(公告)日：2022-01-27

申请号：US17496564

申请日：2021-10-07

申请人： Micron Technology, Inc.

发明人： Michael Mutch ,  Ashonita A. Chavan ,  Sameer Chhajed ,  Beth R. Cook ,  Kamal Kumar Muthukrishnan ,  Durai Vishak Nirmal Ramaswamy ,  Lance Williamson

IPC分类号： G11C11/22 ,  H01L49/02 ,  H01L27/11502

摘要： A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.

公开(公告)号：US10950384B2

公开(公告)日：2021-03-16

申请号：US15691541

申请日：2017-08-30

申请人： Micron Technology, Inc.

发明人： Manuj Nahar ,  Ashonita A. Chavan

IPC分类号： H01F7/06 ,  H01G4/10 ,  H01G4/30 ,  H01L29/66 ,  H01L27/1159 ,  H01L27/11507 ,  H01G4/33 ,  H01L29/78 ,  H01L49/02 ,  H01L21/28 ,  H01L29/51

摘要： A method used in forming an electronic device comprising conductive material and ferroelectric material comprises forming a composite stack comprising multiple metal oxide-comprising insulator materials. At least one of the metal oxide-comprising insulator materials is between and directly against non-ferroelectric insulating materials. The multiple metal oxide-comprising insulator materials are of different composition from that of immediately-adjacent of the non-ferroelectric insulating materials. The composite stack is subjected to a temperature of at least 200° C. After the subjecting, the composite stack comprises multiple ferroelectric metal oxide-comprising insulator materials at least one of which is between and directly against non-ferroelectric insulating materials. After the subjecting, the composite stack is ferroelectric. Conductive material is formed and that is adjacent the composite stack. Devices are also disclosed.

公开(公告)号：US20190189357A1

公开(公告)日：2019-06-20

申请号：US15843278

申请日：2017-12-15

申请人： Micron Technology, Inc.

发明人： Ashonita A. Chavan ,  Beth R. Cook ,  Manuj Nahar ,  Durai Vishak Nirmal Ramaswamy

IPC分类号： H01G4/38 ,  G11C11/22 ,  H01L27/11507

CPC分类号： H01G4/385 ,  G11C11/221 ,  H01L27/11507

摘要： Some embodiments include an apparatus having horizontally-spaced bottom electrodes supported by a supporting structure. Leaker device material is directly against the bottom electrodes. Insulative material is over the bottom electrodes, and upper electrodes are over the insulative material. Plate material extends across the upper electrodes and couples the upper electrodes to one another. The plate material is directly against the leaker device material. The leaker device material electrically couples the bottom electrodes to the plate material, and may be configured to discharge at least a portion of excess charge from the bottom electrodes to the plate material. Some embodiments include methods of forming apparatuses which include capacitors having bottom electrodes and top electrodes, with the top electrodes being electrically coupled to one another through a conductive plate. Leaker devices are formed to electrically couple the bottom electrodes to the conductive plate.

公开(公告)号：US10147474B2

公开(公告)日：2018-12-04

申请号：US15854334

申请日：2017-12-26

申请人： Micron Technology, Inc.

发明人： Steven C. Nicholes ,  Ashonita A. Chavan ,  Matthew N. Rocklein

IPC分类号： G11C11/22 ,  H01L27/11502 ,  G11C14/00 ,  G11C11/56 ,  G11C13/04 ,  H01L27/11507 ,  H01L49/02

摘要： Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.

公开(公告)号：US20180197869A1

公开(公告)日：2018-07-12

申请号：US15912826

申请日：2018-03-06

申请人： Micron Technology, Inc.

发明人： Ashonita A. Chavan ,  Durai Vishak Nirmal Ramaswamy

IPC分类号： H01L27/11507

CPC分类号： H01L27/11507 ,  H01L27/11514

摘要： A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in support material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. A capacitor insulator is formed laterally outward of the upper and lower capacitor electrode linings. Conductive material is formed laterally outward of the capacitor insulator to comprise a shared capacitor electrode that is shared by vertically opposed capacitors in individual of the pairs of vertically opposed capacitors. Other methods and structure independent of method of manufacture are disclosed.

公开(公告)号：US20180006044A1

公开(公告)日：2018-01-04

申请号：US15691806

申请日：2017-08-31

申请人： Micron Technology, Inc.

发明人： Ashonita A. Chavan ,  Alessandro Calderoni ,  D.V. Nirmal Ramaswamy

IPC分类号： H01L27/11507 ,  H01L29/423 ,  H01L49/02

摘要： Ferroelectric memory and methods of forming the same are provided. An example memory cell can include a buried recessed access device (BRAD) formed in a substrate and a ferroelectric capacitor formed on the BRAD.

公开(公告)号：US20150311217A1

公开(公告)日：2015-10-29

申请号：US14263610

申请日：2014-04-28

申请人： Micron Technology, Inc.

发明人： Ashonita A. Chavan ,  Alessandro Calderoni ,  D.V. Nirmal Ramaswamy

IPC分类号： H01L27/115

CPC分类号： H01L27/11507 ,  H01L27/10876 ,  H01L28/90 ,  H01L29/4236

摘要： Ferroelectric memory and methods of forming the same are provided. An example memory cell can include a buried recessed access device (BRAD) formed in a substrate and a ferroelectric capacitor formed on the BRAD.

摘要翻译： 提供铁电存储器及其形成方法。 示例性存储单元可以包括形成在衬底中的埋入式存取器件（BRAD）和形成在BRAD上的铁电电容器。

公开(公告)号：US20240164114A1

公开(公告)日：2024-05-16

申请号：US18522637

申请日：2023-11-29

申请人： Micron Technology, Inc.

发明人： Hung-Wei Liu ,  Vassil N. Antonov ,  Ashonita A. Chavan ,  Darwin Franseda Fan ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Masihhur R. Laskar ,  Albert Liao ,  Xue-Feng Lin ,  Manuj Nahar ,  Irina V. Vasilyeva

IPC分类号： H10B53/20 ,  H01L21/223 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H10B51/20 ,  H10B51/30 ,  H10B53/30

CPC分类号： H10B53/20 ,  H01L21/223 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/7827 ,  H10B51/20 ,  H10B51/30 ,  H10B53/30

摘要： A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

公开(公告)号：US11856790B2

公开(公告)日：2023-12-26

申请号：US18072546

申请日：2022-11-30

申请人： Micron Technology, Inc.

发明人： Ashonita A. Chavan ,  Durai Vishak Nirmal Ramaswamy ,  Manuj Nahar

IPC分类号： H01L29/78 ,  H10B53/30 ,  H01L21/28 ,  H10B51/30 ,  H01L21/02 ,  H01L49/02 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC分类号： H10B53/30 ,  H01L21/02164 ,  H01L21/28088 ,  H01L21/28097 ,  H01L28/55 ,  H01L28/60 ,  H01L29/40111 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/30

摘要： A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 1×102 Siemens/cm. The composite stack is used to render the non-ferroelectric metal oxide-comprising insulator material to be ferroelectric. Conductive material is formed over the composite stack and the insulator material. Ferroelectric capacitors and ferroelectric field effect transistors independent of method of manufacture are also disclosed.