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    Electronic device comprising conductive material and ferroelectric material
    2.
    发明授权
    Electronic device comprising conductive material and ferroelectric material 有权

    公开(公告)号：US11469043B2

    公开(公告)日：2022-10-11

    申请号：US17183285

    申请日：2021-02-23

    Applicant: Micron Technology, Inc.

    Inventor： Manuj Nahar ,  Ashonita A. Chavan

    IPC: H01L21/02 ,  H01G4/10 ,  H01G4/30 ,  H01L29/66 ,  H01L27/1159 ,  H01L27/11507 ,  H01G4/33 ,  H01L29/78 ,  H01L49/02 ,  H01L21/28 ,  H01L29/51 ,  H01G4/40

    Abstract: A method used in forming an electronic device comprising conductive material and ferroelectric material comprises forming a composite stack comprising multiple metal oxide-comprising insulator materials. At least one of the metal oxide-comprising insulator materials is between and directly against non-ferroelectric insulating materials. The multiple metal oxide-comprising insulator materials are of different composition from that of immediately-adjacent of the non-ferroelectric insulating materials. The composite stack is subjected to a temperature of at least 200° C. After the subjecting, the composite stack comprises multiple ferroelectric metal oxide-comprising insulator materials at least one of which is between and directly against non-ferroelectric insulating materials. After the subjecting, the composite stack is ferroelectric. Conductive material is formed and that is adjacent the composite stack. Devices are also disclosed.

    Method used in forming an electronic device comprising conductive material and ferroelectric material
    4.
    发明授权
    Method used in forming an electronic device comprising conductive material and ferroelectric material 有权

    公开(公告)号：US10950384B2

    公开(公告)日：2021-03-16

    申请号：US15691541

    申请日：2017-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Manuj Nahar ,  Ashonita A. Chavan

    IPC: H01F7/06 ,  H01G4/10 ,  H01G4/30 ,  H01L29/66 ,  H01L27/1159 ,  H01L27/11507 ,  H01G4/33 ,  H01L29/78 ,  H01L49/02 ,  H01L21/28 ,  H01L29/51

    Abstract: A method used in forming an electronic device comprising conductive material and ferroelectric material comprises forming a composite stack comprising multiple metal oxide-comprising insulator materials. At least one of the metal oxide-comprising insulator materials is between and directly against non-ferroelectric insulating materials. The multiple metal oxide-comprising insulator materials are of different composition from that of immediately-adjacent of the non-ferroelectric insulating materials. The composite stack is subjected to a temperature of at least 200° C. After the subjecting, the composite stack comprises multiple ferroelectric metal oxide-comprising insulator materials at least one of which is between and directly against non-ferroelectric insulating materials. After the subjecting, the composite stack is ferroelectric. Conductive material is formed and that is adjacent the composite stack. Devices are also disclosed.

    Methods of Incorporating Leaker Devices into Capacitor Configurations to Reduce Cell Disturb
    5.
    发明申请
    Methods of Incorporating Leaker Devices into Capacitor Configurations to Reduce Cell Disturb 审中-公开

    公开(公告)号：US20190189357A1

    公开(公告)日：2019-06-20

    申请号：US15843278

    申请日：2017-12-15

    Applicant: Micron Technology, Inc.

    Inventor： Ashonita A. Chavan ,  Beth R. Cook ,  Manuj Nahar ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01G4/38 ,  G11C11/22 ,  H01L27/11507

    CPC classification number: H01G4/385 ,  G11C11/221 ,  H01L27/11507

    Abstract: Some embodiments include an apparatus having horizontally-spaced bottom electrodes supported by a supporting structure. Leaker device material is directly against the bottom electrodes. Insulative material is over the bottom electrodes, and upper electrodes are over the insulative material. Plate material extends across the upper electrodes and couples the upper electrodes to one another. The plate material is directly against the leaker device material. The leaker device material electrically couples the bottom electrodes to the plate material, and may be configured to discharge at least a portion of excess charge from the bottom electrodes to the plate material. Some embodiments include methods of forming apparatuses which include capacitors having bottom electrodes and top electrodes, with the top electrodes being electrically coupled to one another through a conductive plate. Leaker devices are formed to electrically couple the bottom electrodes to the conductive plate.

    Memory cells and semiconductor devices including ferroelectric materials
    6.
    发明授权
    Memory cells and semiconductor devices including ferroelectric materials 有权

    公开(公告)号：US10147474B2

    公开(公告)日：2018-12-04

    申请号：US15854334

    申请日：2017-12-26

    Applicant: Micron Technology, Inc.

    Inventor： Steven C. Nicholes ,  Ashonita A. Chavan ,  Matthew N. Rocklein

    IPC: G11C11/22 ,  H01L27/11502 ,  G11C14/00 ,  G11C11/56 ,  G11C13/04 ,  H01L27/11507 ,  H01L49/02

    Abstract: Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.

    Methods Of Forming An Array Comprising Pairs Of Vertically Opposed Capacitors And Arrays Comprising Pairs Of Vertically Opposed Capacitors
    7.
    发明申请
    Methods Of Forming An Array Comprising Pairs Of Vertically Opposed Capacitors And Arrays Comprising Pairs Of Vertically Opposed Capacitors 审中-公开

    公开(公告)号：US20180197869A1

    公开(公告)日：2018-07-12

    申请号：US15912826

    申请日：2018-03-06

    Applicant: Micron Technology, Inc.

    Inventor： Ashonita A. Chavan ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L27/11507

    CPC classification number: H01L27/11507 ,  H01L27/11514

    Abstract: A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in support material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. A capacitor insulator is formed laterally outward of the upper and lower capacitor electrode linings. Conductive material is formed laterally outward of the capacitor insulator to comprise a shared capacitor electrode that is shared by vertically opposed capacitors in individual of the pairs of vertically opposed capacitors. Other methods and structure independent of method of manufacture are disclosed.

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