Invention Grant
- Patent Title: Semiconductor processing systems with in-situ electrical bias
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Application No.: US17185231Application Date: 2021-02-25
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Publication No.: US11894240B2Publication Date: 2024-02-06
- Inventor: David Hurley , Ioan Domsa , Ian Colgan , Gerhardus Van Der Linde , Patrick Hughes , Maciej Burel , Barry Clarke , Mihaela Ioana Popovici , Lars-Ake Ragnarsson , Gerrit J. Leusink , Robert Clark , Dina Triyoso
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: TOKYO ELECTRON LIMITED
- Current Assignee: TOKYO ELECTRON LIMITED
- Current Assignee Address: JP Tokyo
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/326
- IPC: H01L21/326 ; H01L21/04 ; H01L21/42 ; H01L21/02
Abstract:
A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.
Public/Granted literature
- US20210313189A1 SEMICONDUCTOR PROCESSING SYSTEMS WITH IN-SITU ELECTRICAL BIAS Public/Granted day:2021-10-07
Information query
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