公开(公告)号：US20240096638A1

公开(公告)日：2024-03-21

申请号：US17946609

申请日：2022-09-16

Applicant: Tokyo Electron Limited

Inventor： Shan Hu ,  Henan Zhang ,  Sangita Kumari ,  Peter Delia ,  Robert Clark

IPC: H01L21/311 ,  H01L21/306 ,  H01L21/3213

CPC classification number: H01L21/31111 ,  H01L21/30604 ,  H01L21/32134

Abstract: Embodiments of a wet etch process and methods are disclosed herein to provide uniform wet etching of material formed within features (e.g., trenches, holes, slits, etc.), and on more planar areas of a patterned substrate, when a critical dimension (CD) of the features is relatively small compared to the more planar areas of the patterned substrate. In the present disclosure, uniform wet etching is provided by ensuring that wall surfaces adjacent to the material being etched exhibit a neutral surface charge when exposed to the etch solution used to etch the material.

公开(公告)号：US11769677B2

公开(公告)日：2023-09-26

申请号：US17682202

申请日：2022-02-28

Applicant: Tokyo Electron Limited

Inventor： Kandabara Tapily ,  Robert Clark

IPC: H01L21/67 ,  H01L21/66 ,  H01L21/311 ,  H01L21/02 ,  C23C16/06 ,  C23C16/40 ,  C23C16/02 ,  C23C16/56

CPC classification number: H01L21/67167 ,  C23C16/0272 ,  C23C16/06 ,  C23C16/40 ,  C23C16/56 ,  H01L21/02118 ,  H01L21/31116 ,  H01L21/67196 ,  H01L21/67207 ,  H01L21/67253 ,  H01L22/20 ,  H01L21/0228 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/67069

Abstract: A substrate processing method includes (a) providing a substrate in a substrate processing tool, the substrate containing an exposed surface of a first material layer and an exposed surface of a second material layer; (b) forming a self-assembled monolayer (SAM) on the substrate in a first substrate processing chamber (SPC); (c) transferring the substrate from the first SPC through a substrate transfer chamber to a second SPC; (d) depositing a film selectively on the first material layer and film nuclei on the SAM in the second SPC; (e) transferring, after selectively depositing the film on the first material layer, the substrate from the second SPC through the substrate transfer chamber to a third SPC; (f) removing the film nuclei from the SAM by etching in the third SPC; and repeating (b), (c), (d), (e) and (f) sequentially at least once.

公开(公告)号：US11621190B2

公开(公告)日：2023-04-04

申请号：US17334389

申请日：2021-05-28

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  David O'Meara ,  Nicholas Joy ,  Gyanaranjan Pattanaik ,  Robert Clark ,  Kandabara Tapily ,  Takahiro Hakamata ,  Cory Wajda ,  Gerrit Leusink

IPC: H01L21/768 ,  H01L21/02

Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.

公开(公告)号：US11594451B2

公开(公告)日：2023-02-28

申请号：US17140310

申请日：2021-01-04

Applicant: Tokyo Electron Limited

Inventor： Robert Clark ,  Kandabara Tapily ,  Kai-Hung Yu

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/66 ,  H01L21/677 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  G05B13/02 ,  G05B19/418 ,  C23C14/24 ,  C23C14/34 ,  H01J37/32

Abstract: A method of preparing a self-aligned via on a semiconductor workpiece includes using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules. The integrated sequence of processing steps include receiving the workpiece into the common manufacturing platform, the workpiece having a pattern of metal features in a dielectric layer wherein exposed surfaces of the metal features and exposed surfaces of the dielectric layer together define an upper planar surface; selectively etching the metal features to form a recess pattern by recessing the exposed surfaces of the metal features beneath the exposed surfaces of the dielectric layer using one of the one or more etching modules; and depositing an etch stop layer over the recess pattern using one of the one or more film-forming modules.

公开(公告)号：US20220285163A1

公开(公告)日：2022-09-08

申请号：US17194421

申请日：2021-03-08

Applicant: Tokyo Electron Limited

Inventor： Robert Clark

IPC: H01L21/3065 ,  H01J37/32 ,  H01J37/305

Abstract: In one example, a method of processing a substrate includes loading the substrate in a process chamber, where the substrate includes a metal oxide containing film to be etched. The method further includes performing of an atomic layer etching including a plurality of cyclic processes, each of the plurality of cyclic processes including exposing the metal oxide containing film to a first gas stream including boron trichloride (BCl3), and exposing the metal oxide containing film to a second gas stream including borane, amine, alcohol, carboxylic acid, carboxamide, or beta-diketone reagent.

公开(公告)号：US20220238323A1

公开(公告)日：2022-07-28

申请号：US17161033

申请日：2021-01-28

Applicant: Tokyo Electron Limited

Inventor： Robert Clark

IPC: H01L21/02 ,  H01L21/768 ,  C23C16/40 ,  C23C16/06 ,  C23C16/455

Abstract: A method is described for an area selective deposition (ASD) process that is a dielectric on dielectric (DoD) ASD process performed over a major surface of a semiconductor substrate. The substrate comprises a conductive material embedded in a first dielectric layer, and the major surface comprises a conductive surface and a dielectric surface of the first dielectric layer. In this method, a metal-containing capping layer is formed selectively over the dielectric surface of the first dielectric layer. In a subsequent process step, a second dielectric layer is formed from the metal-containing capping layer. Hence, the DoD ASD process forms the second dielectric layer selectively over the dielectric surface of the first dielectric layer. The dielectric material for the second dielectric layer may be deposited by performing, for example, a catalytic decomposition of a precursor gas in a surface reaction where the catalyst is obtained from the selectively formed metal-containing layer.

公开(公告)号：US11302588B2

公开(公告)日：2022-04-12

申请号：US16356388

申请日：2019-03-18

Applicant: Tokyo Electron Limited

Inventor： Robert Clark ,  Kandabara Tapily ,  Jason Mehigan

IPC: H01L21/66 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/67 ,  H01L21/677 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/324

Abstract: A method is provided for area-selective deposition on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting one or more film-forming modules, one or more etching modules, and one or more transfer modules. A workpiece having a target surface of a first material and a non-target surface of a second material different than the first material is received into the common manufacturing platform. An additive material is deposited on the workpiece with selectivity that results in the additive material forming on the target surface at a higher deposition rate than on the non-target surface, followed by etching to expose the non-target surface. The integrated sequence of processing steps is executed within the common manufacturing platform without leaving the controlled environment and the transfer modules are used to transfer the workpiece between the processing modules while maintaining the workpiece within the controlled environment.

公开(公告)号：US10923394B2

公开(公告)日：2021-02-16

申请号：US16357724

申请日：2019-03-19

Applicant: Tokyo Electron Limited

Inventor： Robert Clark ,  Kandabara Tapily ,  Kai-Hung Yu

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/67 ,  H01L21/66 ,  H01L21/677 ,  H01L21/285 ,  H01L21/311 ,  G05B13/02 ,  G05B19/418 ,  C23C14/24 ,  C23C14/34 ,  H01J37/32

Abstract: A method for forming a fully self-aligned via is provided. A workpiece having a pattern of features in a dielectric layer is received into a common manufacturing platform. Metal caps are deposited on the metal features, and a barrier layer is deposited on the metal caps. A first dielectric layer is added to exposed dielectric material. The barrier layer is removed and an etch stop layer is added on the exposed surfaces of the first dielectric layer and the metal caps. Additional dielectric material is added on top of the etch stop layer, then both the additional dielectric material and a portion of the etch stop layer are etched to form a feature to be filled with metal material. An integrated sequence of processing steps is executed within one or more common manufacturing platforms to provide controlled environments. Transfer modules transfer the workpiece between processing modules within and between controlled environments.

公开(公告)号：US20190295870A1

公开(公告)日：2019-09-26

申请号：US16355579

申请日：2019-03-15

Applicant: Tokyo Electron Limited

Inventor： Kandabara Tapily ,  Robert Clark

IPC: H01L21/67 ,  H01L21/66 ,  H01L21/311 ,  H01L21/02 ,  C23C16/06 ,  C23C16/40 ,  C23C16/02 ,  C23C16/56

Abstract: A substrate processing tool configured for performing integrated substrate processing and substrate metrology, and methods of processing a substrate. The substrate processing tool includes a substrate transfer chamber, a plurality of substrate processing chambers coupled to the substrate transfer chamber, and a substrate metrology module coupled to the substrate transfer chamber. A substrate processing method includes processing a substrate in a first substrate processing chamber of a substrate processing tool, transferring the substrate from the first substrate processing chamber through a substrate transfer chamber to a substrate metrology module in the substrate processing tool, performing metrology on the substrate in the substrate metrology module, transferring the substrate from the substrate metrology module to a second substrate processing chamber through the substrate transfer chamber, and processing the substrate in the second substrate processing chamber.

公开(公告)号：US20190295845A1

公开(公告)日：2019-09-26

申请号：US16356388

申请日：2019-03-18

Applicant: Tokyo Electron Limited

Inventor： Robert Clark ,  Kandabara Tapily ,  Jason Mehigan

IPC: H01L21/02 ,  H01L21/677 ,  H01L21/67 ,  H01L21/66

Abstract: A method is provided for area-selective deposition on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting one or more film-forming modules, one or more etching modules, and one or more transfer modules. A workpiece having a target surface of a first material and a non-target surface of a second material different than the first material is received into the common manufacturing platform. An additive material is deposited on the workpiece with selectivity that results in the additive material forming on the target surface at a higher deposition rate than on the non-target surface, followed by etching to expose the non-target surface. The integrated sequence of processing steps is executed within the common manufacturing platform without leaving the controlled environment and the transfer modules are used to transfer the workpiece between the processing modules while maintaining the workpiece within the controlled environment.