Invention Grant
- Patent Title: V-NAND stacks with dipole regions
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Application No.: US17329484Application Date: 2021-05-25
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Publication No.: US11997849B2Publication Date: 2024-05-28
- Inventor: Yong Yang , Jacqueline S. Wrench , Yixiong Yang , Pradeep K. Subrahmanyan , Srinivas Gandikota
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Servilla Whitney LLC
- Main IPC: H10B41/27
- IPC: H10B41/27 ; G11C5/06 ; H01L21/8234 ; H10B43/27

Abstract:
A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.
Public/Granted literature
- US20220384469A1 V-NAND STACKS WITH DIPOLE REGIONS Public/Granted day:2022-12-01
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